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Support exec multi-cycle for div/mul

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This commit is contained in:
wgulian3
2020-02-13 13:17:46 -05:00
parent c1bd731d7f
commit 8318aff69f
8 changed files with 100 additions and 58 deletions
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51
rtl/VX_writeback.v
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@@ -14,10 +14,10 @@ module VX_writeback (
// Actual WB to GPR
VX_wb_inter VX_writeback_inter,
output wire no_slot_mem
output wire no_slot_mem,
output wire no_slot_exec
);
VX_wb_inter VX_writeback_tempp();
wire exec_wb = (VX_inst_exec_wb.wb != 0) && (|VX_inst_exec_wb.wb_valid);
@@ -25,38 +25,39 @@ module VX_writeback (
wire csr_wb = (VX_csr_wb.wb != 0) && (|VX_csr_wb.valid);
assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
assign no_slot_exec = exec_wb && (csr_wb);
assign VX_writeback_tempp.write_data = exec_wb ? VX_inst_exec_wb.alu_result :
csr_wb ? VX_csr_wb.csr_result :
assign VX_writeback_tempp.write_data = csr_wb ? VX_csr_wb.csr_result :
exec_wb ? VX_inst_exec_wb.alu_result :
mem_wb ? VX_mem_wb.loaded_data :
0;
assign VX_writeback_tempp.wb_valid = exec_wb ? VX_inst_exec_wb.wb_valid :
csr_wb ? VX_csr_wb.valid :
assign VX_writeback_tempp.wb_valid = csr_wb ? VX_csr_wb.valid :
exec_wb ? VX_inst_exec_wb.wb_valid :
mem_wb ? VX_mem_wb.wb_valid :
0;
assign VX_writeback_tempp.rd = exec_wb ? VX_inst_exec_wb.rd :
csr_wb ? VX_csr_wb.rd :
assign VX_writeback_tempp.rd = csr_wb ? VX_csr_wb.rd :
exec_wb ? VX_inst_exec_wb.rd :
mem_wb ? VX_mem_wb.rd :
0;
assign VX_writeback_tempp.wb = exec_wb ? VX_inst_exec_wb.wb :
csr_wb ? VX_csr_wb.wb :
assign VX_writeback_tempp.wb = csr_wb ? VX_csr_wb.wb :
exec_wb ? VX_inst_exec_wb.wb :
mem_wb ? VX_mem_wb.wb :
0;
assign VX_writeback_tempp.wb_warp_num = exec_wb ? VX_inst_exec_wb.wb_warp_num :
csr_wb ? VX_csr_wb.warp_num :
assign VX_writeback_tempp.wb_warp_num = csr_wb ? VX_csr_wb.warp_num :
exec_wb ? VX_inst_exec_wb.wb_warp_num :
mem_wb ? VX_mem_wb.wb_warp_num :
0;
assign VX_writeback_tempp.wb_pc = exec_wb ? VX_inst_exec_wb.exec_wb_pc :
csr_wb ? 32'hdeadbeef :
assign VX_writeback_tempp.wb_pc = csr_wb ? 32'hdeadbeef :
exec_wb ? VX_inst_exec_wb.exec_wb_pc :
mem_wb ? VX_mem_wb.mem_wb_pc :
32'hdeadbeef;
@@ -65,17 +66,6 @@ module VX_writeback (
wire[`NT-1:0][31:0] use_wb_data;
reg prev_is_mem;
always @(posedge clk, posedge reset) begin
if (reset)
begin
prev_is_mem = 0;
end begin
prev_is_mem = mem_wb && !no_slot_mem;
end
end
VX_generic_register #(.N(39 + `NW_M1 + 1 + `NT*33)) wb_register(
.clk (clk),
.reset(reset),
@@ -85,14 +75,9 @@ module VX_writeback (
.out ({use_wb_data , VX_writeback_inter.wb_valid, VX_writeback_inter.rd, VX_writeback_inter.wb, VX_writeback_inter.wb_warp_num, VX_writeback_inter.wb_pc})
);
`ifdef SYN
assign VX_writeback_inter.write_data = prev_is_mem ? VX_writeback_tempp.write_data : use_wb_data;
`else
assign VX_writeback_inter.write_data = use_wb_data;
`endif
assign VX_writeback_inter.write_data = use_wb_data;
endmodule // VX_writeback
endmodule : VX_writeback // VX_writeback