Support exec multi-cycle for div/mul
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@@ -12,7 +12,10 @@ module VX_execute_unit (
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// JAL Response
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VX_jal_response_inter VX_jal_rsp,
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// Branch Response
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VX_branch_response_inter VX_branch_rsp
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VX_branch_response_inter VX_branch_rsp,
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input wire no_slot_exec,
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output wire out_delay
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);
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@@ -41,10 +44,13 @@ module VX_execute_unit (
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wire[`NT_M1:0][31:0] alu_result;
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wire[`NT_M1:0] alu_stall;
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genvar index_out_reg;
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generate
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for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1) begin : alu_defs
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VX_alu vx_alu(
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.clk(clk),
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.reset(reset),
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// .in_reg_data (in_reg_data[1:0]),
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.in_1 (in_a_reg_data[index_out_reg]),
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.in_2 (in_b_reg_data[index_out_reg]),
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@@ -53,11 +59,17 @@ module VX_execute_unit (
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.in_upper_immed(in_upper_immed),
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.in_alu_op (in_alu_op),
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.in_curr_PC (in_curr_PC),
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.out_alu_result(alu_result[index_out_reg])
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.out_alu_result(alu_result[index_out_reg]),
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.out_alu_stall(alu_stall[index_out_reg])
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);
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end
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endgenerate
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wire internal_stall;
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assign internal_stall = |alu_stall;
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assign out_delay = no_slot_exec || internal_stall;
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wire [$clog2(`NT)-1:0] jal_branch_use_index;
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wire jal_branch_found_valid;
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@@ -103,7 +115,7 @@ module VX_execute_unit (
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// Actual Writeback
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assign VX_inst_exec_wb.rd = VX_exec_unit_req.rd;
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assign VX_inst_exec_wb.wb = VX_exec_unit_req.wb;
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assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid;
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assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid && !internal_stall;
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assign VX_inst_exec_wb.wb_warp_num = VX_exec_unit_req.warp_num;
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assign VX_inst_exec_wb.alu_result = VX_exec_unit_req.jal ? duplicate_PC_data : alu_result;
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@@ -163,4 +175,4 @@ module VX_execute_unit (
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// assign out_is_csr = VX_exec_unit_req.is_csr;
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// assign out_csr_address = VX_exec_unit_req.csr_address;
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endmodule
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endmodule : VX_execute_unit
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