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Support exec multi-cycle for div/mul

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wgulian3
2020-02-13 13:17:46 -05:00
parent c1bd731d7f
commit 8318aff69f
8 changed files with 100 additions and 58 deletions
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42
rtl/VX_alu.v
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@@ -1,6 +1,8 @@
`include "VX_define.v"
module VX_alu(
input wire clk,
input wire reset,
input wire[31:0] in_1,
input wire[31:0] in_2,
input wire in_rs2_src,
@@ -8,9 +10,11 @@ module VX_alu(
input wire[19:0] in_upper_immed,
input wire[4:0] in_alu_op,
input wire[31:0] in_curr_PC,
output reg[31:0] out_alu_result
output reg[31:0] out_alu_result,
output reg out_alu_stall
);
localparam div_pipeline_len = 3;
`ifdef SYN_FUNC
wire which_in2;
@@ -25,23 +29,25 @@ module VX_alu(
wire[31:0] signed_div_result;
wire[31:0] signed_rem_result;
reg [15:0] inst_delay;
reg [15:0] inst_delay_count;
assign out_alu_stall = inst_delay != 0 || inst_delay_count != 0;
assign which_in2 = in_rs2_src == `RS2_IMMED;
assign ALU_in1 = in_1;
assign ALU_in2 = which_in2 ? in_itype_immed : in_2;
assign upper_immed = {in_upper_immed, {12{1'b0}}};
VX_divide #(
.WIDTHN(32),
.WIDTHD(32),
.SPEED("HIGHEST"),
.PIPELINE(0)
.PIPELINE(div_pipeline_len)
) unsigned_div (
.clk(0),
.clock(clk),
.aclr(0),
.clken(1), // TODO this could be disabled on inactive instructions
.numer(ALU_in1),
@@ -56,9 +62,9 @@ module VX_alu(
.NREP("SIGNED"),
.DREP("SIGNED"),
.SPEED("HIGHEST"),
.PIPELINE(0)
.PIPELINE(div_pipeline_len)
) signed_div (
.clk(0),
.clock(clk),
.aclr(0),
.clken(1), // TODO this could be disabled on inactive instructions
.numer(ALU_in1),
@@ -101,6 +107,7 @@ module VX_alu(
`MULH: out_alu_result = mult_result[63:32];
`MULHSU: out_alu_result = mult_result[63:32];
`MULHU: out_alu_result = mult_result[63:32];
// TODO profitable to roll these exceptional cases into inst_delay to avoid pipeline when possible?
`DIV: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : signed_div_result;
`DIVU: out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : unsigned_div_result;
`REM: out_alu_result = (ALU_in2 == 0) ? ALU_in1 : signed_rem_result;
@@ -109,6 +116,25 @@ module VX_alu(
endcase // in_alu_op
end
always @(*) begin
case(in_alu_op)
`DIV,
`DIVU,
`REM,
`REMU: inst_delay = div_pipeline_len;
default: inst_delay = 0;
endcase // in_alu_op
end
always @(posedge clk or posedge reset) begin
if (reset)
inst_delay_count <= 0;
else if (inst_delay_count > 0)
inst_delay_count <= inst_delay_count - 1;
else if (inst_delay != 0)
inst_delay_count <= inst_delay - 1;
end
`else
wire which_in2;
@@ -169,4 +195,4 @@ module VX_alu(
end
`endif
endmodule
endmodule : VX_alu