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fpga fixes

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This commit is contained in:
Blaise Tine
2020-06-27 14:03:20 -07:00
parent d4e006d92d
commit 8302641510
28 changed files with 589 additions and 447 deletions
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169
hw/rtl/libs/VX_divide.v
View File

@@ -1,14 +1,14 @@
`include "VX_define.vh"
module VX_divide #(
parameter WIDTHN=1,
parameter WIDTHD=1,
parameter NREP="UNSIGNED",
parameter DREP="UNSIGNED",
parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
parameter PIPELINE=0
parameter WIDTHN = 1,
parameter WIDTHD = 1,
parameter REP = "UNSIGNED",
parameter PIPELINE = 0
) (
input clock, aclr, clken,
input wire clk,
input wire reset,
input wire clken,
input [WIDTHN-1:0] numer,
input [WIDTHD-1:0] denom,
@@ -17,105 +17,86 @@ module VX_divide #(
output reg [WIDTHD-1:0] remainder
);
generate
`ifdef QUARTUS
if (NREP != DREP) begin
different_nrep_drep_not_yet_supported non_existing_module();
end
lpm_divide #(
.LPM_WIDTHN(WIDTHN),
.LPM_WIDTHD(WIDTHD),
.LPM_NREPRESENTATION(REP),
.LPM_DREPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
.MAXIMIZE_SPEED(9)
) quartus_divider (
.clock(clk),
.aclr(reset),
.clken(clken),
.numer(numer),
.denom(denom),
.quotient(quotient),
.remain(remainder)
);
`ifdef QUARTUS
`else
localparam lpm_speed=SPEED == "HIGHEST" ? 9 : 5;
wire [WIDTHN-1:0] numer_pipe_end;
wire [WIDTHD-1:0] denom_pipe_end;
lpm_divide #(
.LPM_WIDTHN(WIDTHN),
.LPM_WIDTHD(WIDTHD),
.LPM_NREPRESENTATION(NREP),
.LPM_DREPRESENTATION(DREP),
.LPM_PIPELINE(PIPELINE),
.LPM_REMAINDERPOSITIVE("FALSE"), // emulate verilog % operator
.MAXIMIZE_SPEED(lpm_speed)
) quartus_divider (
.clock(clock),
.aclr(aclr),
.clken(clken),
.numer(numer),
.denom(denom),
.quotient(quotient),
.remain(remainder)
);
if (PIPELINE == 0) begin
assign numer_pipe_end = numer;
assign denom_pipe_end = denom;
end else begin
reg [WIDTHN-1:0] numer_pipe [0:PIPELINE-1];
reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
`else
wire [WIDTHN-1:0] numer_pipe_end;
wire [WIDTHD-1:0] denom_pipe_end;
if (PIPELINE == 0) begin
assign numer_pipe_end = numer;
assign denom_pipe_end = denom;
end else begin
reg [WIDTHN-1:0] numer_pipe [0:PIPELINE-1];
reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
always @(posedge clock or posedge aclr) begin
if (aclr) begin
numer_pipe[i+1] <= 0;
denom_pipe[i+1] <= 0;
end
else if (clken) begin
numer_pipe[i+1] <= numer_pipe[i];
denom_pipe[i+1] <= denom_pipe[i];
end
end
end
always @(posedge clock or posedge aclr) begin
if (aclr) begin
numer_pipe[0] <= 0;
denom_pipe[0] <= 0;
genvar i;
for (i = 0; i < PIPELINE; i++) begin
always @(posedge clk) begin
if (reset) begin
numer_pipe[i] <= 0;
denom_pipe[i] <= 0;
end
else if (clken) begin
numer_pipe[0] <= numer;
denom_pipe[0] <= denom;
end
end
assign numer_pipe_end = numer_pipe[PIPELINE-1];
assign denom_pipe_end = denom_pipe[PIPELINE-1];
end
/* * * * * * * * * * * * * * * * * * * * * * */
/* Do the actual fallback computation here */
/* * * * * * * * * * * * * * * * * * * * * * */
if (NREP == "SIGNED") begin
always @(*) begin
if (denom_pipe_end == 0) begin
quotient = 32'hffffffff;
remainder = numer_pipe_end;
end
else if (denom_pipe_end == 32'hffffffff
&& numer_pipe_end == 32'h80000000) begin
// this edge case kills verilator in some cases by causing a division
// overflow exception. INT_MIN / -1 (on x86)
quotient = 0;
remainder = 0;
end
else begin
quotient = $signed(numer_pipe_end) / $signed(denom_pipe_end);
remainder = $signed(numer_pipe_end) % $signed(denom_pipe_end);
if (i == 0) begin
numer_pipe[0] <= 0;
denom_pipe[0] <= 0;
end else begin
numer_pipe[i] <= numer_pipe[i-1];
denom_pipe[i] <= denom_pipe[i-1];
end
end
end
end
else begin
assign quotient = (denom_pipe_end == 0) ? 32'hffffffff : numer_pipe_end/denom_pipe_end;
assign remainder = (denom_pipe_end == 0) ? numer_pipe_end : numer_pipe_end%denom_pipe_end;
end
assign numer_pipe_end = numer_pipe[PIPELINE-1];
assign denom_pipe_end = denom_pipe[PIPELINE-1];
end
always @(*) begin
if (denom_pipe_end == 0) begin
quotient = {WIDTHN{1'b1}};
remainder = numer_pipe_end;
end
`ifndef SYNTHESIS
// this edge case kills verilator in some cases by causing a division
// overflow exception. INT_MIN / -1 (on x86)
else if (numer_pipe_end == {1'b1, (WIDTHN-1)'(0)}
&& denom_pipe_end == {WIDTHD{1'b1}}) begin
quotient = 0;
remainder = 0;
end
`endif
else begin
if (REP == "SIGNED") begin
quotient = $signed(numer_pipe_end) / $signed(denom_pipe_end);
remainder = $signed(numer_pipe_end) % $signed(denom_pipe_end);
end else begin
quotient = numer_pipe_end / denom_pipe_end;
remainder = numer_pipe_end % denom_pipe_end;
end
end
end
endgenerate
`endif
endmodule : VX_divide

4
hw/rtl/libs/VX_indexable_queue.v
View File

@@ -28,8 +28,8 @@ module VX_indexable_queue #(
assign empty = (wr_ptr == rd_ptr);
assign full = (wr_a == rd_a) && (wr_ptr[`LOG2UP(SIZE)] != rd_ptr[`LOG2UP(SIZE)]);
assign enqueue = push && ~full;
assign dequeue = ~empty && ~valid[rd_a]; // auto-remove when head is invalid
assign enqueue = push && !full;
assign dequeue = !empty && !valid[rd_a]; // auto-remove when head is invalid
always @(posedge clk) begin
if (reset) begin

8
hw/rtl/libs/VX_matrix_arbiter.v
View File

@@ -30,17 +30,17 @@ module VX_matrix_arbiter #(
for (i = 0; i < N; ++i) begin
for (j = 0; j < N; ++j) begin
if (j > i) begin
assign pri[j][i] = requests[i] & state[i][j];
assign pri[j][i] = requests[i] && state[i][j];
end
else if (j < i) begin
assign pri[j][i] = requests[i] & ~state[j][i];
assign pri[j][i] = requests[i] && !state[j][i];
end
else begin
assign pri[j][i] = 0;
end
end
assign grant_onehot[i] = requests[i] & ~(| pri[i]);
assign grant_onehot[i] = requests[i] && !(| pri[i]);
end
for (i = 0; i < N; ++i) begin
@@ -50,7 +50,7 @@ module VX_matrix_arbiter #(
state[i][j] <= 0;
end
else begin
state[i][j] <= (state[i][j] || grant_onehot[j]) && ~grant_onehot[i];
state[i][j] <= (state[i][j] || grant_onehot[j]) && !grant_onehot[i];
end
end
end

151
hw/rtl/libs/VX_mult.v
View File

@@ -1,16 +1,14 @@
`include "VX_define.vh"
module VX_mult #(
parameter WIDTHA=1,
parameter WIDTHB=1,
parameter WIDTHP=1,
parameter REP="UNSIGNED",
parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
parameter PIPELINE=0,
parameter FORCE_LE="NO"
parameter WIDTHA = 1,
parameter WIDTHB = 1,
parameter WIDTHP = 1,
parameter REP = "UNSIGNED",
parameter PIPELINE = 0
) (
input clock,
input aclr,
input clk,
input reset,
input clken,
input [WIDTHA-1:0] dataa,
@@ -19,102 +17,67 @@ module VX_mult #(
output reg [WIDTHP-1:0] result
);
generate
`ifdef QUARTUS
`ifdef QUARTUS
lpm_mult #(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
.MAXIMIZE_SPEED(9)
) quartus_mult (
.clock(clk),
.aclr(reset),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
localparam lpm_speed = (SPEED == "HIGHEST") ? 10 : 5;
`else
wire [WIDTHA-1:0] dataa_pipe_end;
wire [WIDTHB-1:0] datab_pipe_end;
if (FORCE_LE == "YES") begin
lpm_mult #(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult (
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
else begin
lpm_mult#(
.LPM_WIDTHA(WIDTHA),
.LPM_WIDTHB(WIDTHB),
.LPM_WIDTHP(WIDTHP),
.LPM_REPRESENTATION(REP),
.LPM_PIPELINE(PIPELINE),
.MAXIMIZE_SPEED(lpm_speed)
) quartus_mult(
.clock(clock),
.aclr(aclr),
.clken(clken),
.dataa(dataa),
.datab(datab),
.result(result)
);
end
if (PIPELINE == 0) begin
assign dataa_pipe_end = dataa;
assign datab_pipe_end = datab;
end else begin
reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
`else
wire [WIDTHA-1:0] dataa_pipe_end;
wire [WIDTHB-1:0] datab_pipe_end;
if (PIPELINE == 0) begin
assign dataa_pipe_end = dataa;
assign datab_pipe_end = datab;
end else begin
reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
genvar i;
for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dataa_pipe[i+1] <= 0;
datab_pipe[i+1] <= 0;
end
else if (clken) begin
dataa_pipe[i+1] <= dataa_pipe[i];
datab_pipe[i+1] <= datab_pipe[i];
end
end
end
always @(posedge clock or posedge aclr) begin
if (aclr) begin
dataa_pipe[0] <= 0;
datab_pipe[0] <= 0;
genvar i;
for (i = 0; i < PIPELINE; i++) begin
always @(posedge clk) begin
if (reset) begin
dataa_pipe[i] <= 0;
datab_pipe[i] <= 0;
end
else if (clken) begin
dataa_pipe[0] <= dataa;
datab_pipe[0] <= datab;
if (i == 0) begin
dataa_pipe[0] <= dataa;
datab_pipe[0] <= datab;
end else begin
dataa_pipe[i] <= dataa_pipe[i-1];
datab_pipe[i] <= datab_pipe[i-1];
end
end
end
assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
assign datab_pipe_end = datab_pipe[PIPELINE-1];
end
/* * * * * * * * * * * * * * * * * * * * * * */
/* Do the actual fallback computation here */
/* * * * * * * * * * * * * * * * * * * * * * */
assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
assign datab_pipe_end = datab_pipe[PIPELINE-1];
end
if (REP == "SIGNED") begin
assign result = $signed(dataa_pipe_end) * $signed(datab_pipe_end);
end
else begin
assign result = dataa_pipe_end * datab_pipe_end;
end
if (REP == "SIGNED") begin
assign result = $signed(dataa_pipe_end) * $signed(datab_pipe_end);
end
else begin
assign result = dataa_pipe_end * datab_pipe_end;
end
`endif
endgenerate
`endif
endmodule: VX_mult