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fpga fixes

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This commit is contained in:
Blaise Tine
2020-06-27 14:03:20 -07:00
parent d4e006d92d
commit 8302641510
28 changed files with 589 additions and 447 deletions
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4
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
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@@ -56,7 +56,7 @@ module VX_cache_dram_req_arb #(
.clk (clk),
.reset (reset),
.dram_req (dram_req_valid && ~dram_req_rw),
.dram_req (dram_req_valid && !dram_req_rw),
.dram_req_addr(dram_req_addr),
.pref_pop (pref_pop),
@@ -91,7 +91,7 @@ module VX_cache_dram_req_arb #(
.dfqq_full (dfqq_full)
);
assign dram_fill_req_ready = ~dfqq_full;
assign dram_fill_req_ready = !dfqq_full;
wire [`BANK_BITS-1:0] dwb_bank;