fpga fixes

2020-06-27 14:03:20 -07:00
parent d4e006d92d
commit 8302641510
28 changed files with 589 additions and 447 deletions
--- a/hw/modelsim/vortex_tb.v
+++ b/hw/modelsim/vortex_tb.v
@@ -140,7 +140,7 @@ reg[31:0]  io_data;
 			clk = 0;
 		end

-		#5 clk <= ~clk;
+		#5 clk <= !clk;
 	end

 endmodule