wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

added config.vh

Browse Source
This commit is contained in:
Blaise Tine
2020-04-16 07:49:19 -04:00
parent c913e542e9
commit 81745f08c9
109 changed files with 1426 additions and 1544 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
hw/rtl/generic_cache/VX_bank.v
View File

@@ -1,5 +1,5 @@
`include "VX_cache_config.v"
`include "VX_define.v"
`include "VX_cache_config.vh"
`include "VX_define.vh"
module VX_bank
#(
// Size of cache in bytes
@@ -60,7 +60,7 @@ module VX_bank
input wire [4:0] bank_rd,
input wire [NUMBER_REQUESTS-1:0][1:0] bank_wb,
input wire [31:0] bank_pc,
input wire [`NW_M1:0] bank_warp_num,
input wire [`NW_BITS-1:0] bank_warp_num,
input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_read,
input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_write,
output wire reqq_full,
@@ -71,7 +71,7 @@ module VX_bank
output wire [`vx_clog2(NUMBER_REQUESTS)-1:0] bank_wb_tid,
output wire [4:0] bank_wb_rd,
output wire [1:0] bank_wb_wb,
output wire [`NW_M1:0] bank_wb_warp_num,
output wire [`NW_BITS-1:0] bank_wb_warp_num,
output wire [`WORD_SIZE_RNG] bank_wb_data,
output wire [31:0] bank_wb_pc,
output wire [31:0] bank_wb_address,
@@ -86,14 +86,14 @@ module VX_bank
// Dram Fill Response
input wire dram_fill_rsp,
input wire [31:0] dram_fill_addr,
input wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dram_fill_rsp_data,
input wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dram_fill_rsp_data,
output wire dram_fill_accept,
// Dram WB Requests
input wire dram_wb_queue_pop,
output wire dram_wb_req,
output wire[31:0] dram_wb_req_addr,
output wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dram_wb_req_data,
output wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dram_wb_req_data,
// Snp Request
input wire snp_req,
@@ -112,7 +112,7 @@ module VX_bank
if (reset) begin
snoop_state <= 0;
end else begin
snoop_state <= (snoop_state | snp_req) && ((FUNC_ID == `LLFUNC_ID) || (FUNC_ID == `L3FUNC_ID));
snoop_state <= (snoop_state | snp_req) && ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID));
end
end
@@ -139,11 +139,11 @@ module VX_bank
wire dfpq_empty;
wire dfpq_full;
wire[31:0] dfpq_addr_st0;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dfpq_filldata_st0;
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dfpq_filldata_st0;
assign dram_fill_accept = !dfpq_full;
VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*`WORD_SIZE)), .SIZE(DFPQ_SIZE)) dfp_queue(
VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_WORDS*`WORD_SIZE)), .SIZE(DFPQ_SIZE)) dfp_queue(
.clk (clk),
.reset (reset),
.push (dram_fill_rsp),
@@ -164,7 +164,7 @@ module VX_bank
wire [`WORD_SIZE_RNG] reqq_req_writeword_st0;
wire [4:0] reqq_req_rd_st0;
wire [1:0] reqq_req_wb_st0;
wire [`NW_M1:0] reqq_req_warp_num_st0;
wire [`NW_BITS-1:0] reqq_req_warp_num_st0;
wire [2:0] reqq_req_mem_read_st0;
wire [2:0] reqq_req_mem_write_st0;
wire [31:0] reqq_req_pc_st0;
@@ -231,7 +231,7 @@ module VX_bank
wire [4:0] mrvq_rd_st0;
wire [1:0] mrvq_wb_st0;
wire [31:0] miss_resrv_pc_st0;
wire [`NW_M1:0] mrvq_warp_num_st0;
wire [`NW_BITS-1:0] mrvq_warp_num_st0;
wire [2:0] mrvq_mem_read_st0;
wire [2:0] mrvq_mem_write_st0;
@@ -241,7 +241,7 @@ module VX_bank
wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid;
wire[4:0] miss_add_rd;
wire[1:0] miss_add_wb;
wire[`NW_M1:0] miss_add_warp_num;
wire[`NW_BITS-1:0] miss_add_warp_num;
wire[2:0] miss_add_mem_read;
wire[2:0] miss_add_mem_write;
@@ -336,7 +336,7 @@ module VX_bank
wire qual_valid_st0;
wire [31:0] qual_addr_st0;
wire [`WORD_SIZE_RNG] qual_writeword_st0;
wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] qual_writedata_st0;
wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] qual_writedata_st0;
wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0;
wire qual_going_to_write_st0;
wire qual_is_snp;
@@ -344,7 +344,7 @@ module VX_bank
wire [`WORD_SIZE_RNG] writeword_st1 [STAGE_1_CYCLES-1:0];
wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] writedata_st1[STAGE_1_CYCLES-1:0];
wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] writedata_st1[STAGE_1_CYCLES-1:0];
wire is_snp_st1 [STAGE_1_CYCLES-1:0];
wire [31:0] pc_st1 [STAGE_1_CYCLES-1:0];
@@ -387,7 +387,7 @@ module VX_bank
reqq_pop ? reqq_req_writeword_st0 :
0;
VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_c0 (
VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_c0 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
@@ -399,7 +399,7 @@ module VX_bank
genvar curr_stage;
generate
for (curr_stage = 1; curr_stage < STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin
VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_SIZE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_cc (
VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
@@ -412,7 +412,7 @@ module VX_bank
wire[`WORD_SIZE_RNG] readword_st1e;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] readdata_st1e;
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] readdata_st1e;
wire[`TAG_SELECT_SIZE_RNG] readtag_st1e;
wire miss_st1e;
wire dirty_st1e;
@@ -421,7 +421,7 @@ module VX_bank
wire [4:0] rd_st1e;
wire [1:0] wb_st1e;
wire [`NW_M1:0] warp_num_st1e;
wire [`NW_BITS-1:0] warp_num_st1e;
wire [2:0] mem_read_st1e;
wire [2:0] mem_write_st1e;
wire [`vx_clog2(NUMBER_REQUESTS)-1:0] tid_st1e;
@@ -488,7 +488,7 @@ module VX_bank
wire valid_st2;
wire[`WORD_SIZE_RNG] writeword_st2;
wire[`WORD_SIZE_RNG] readword_st2;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] readdata_st2;
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] readdata_st2;
wire miss_st2;
wire dirty_st2;
wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2;
@@ -498,7 +498,7 @@ module VX_bank
wire [31:0] pc_st2;
VX_generic_register #(.N( 1+1+1+1+32+`WORD_SIZE+`WORD_SIZE+(`BANK_LINE_SIZE_WORDS * `WORD_SIZE) + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS + 32 + 2)) st_1e_2 (
VX_generic_register #(.N( 1+1+1+1+32+`WORD_SIZE+`WORD_SIZE+(`BANK_LINE_WORDS * `WORD_SIZE) + `REQ_INST_META_SIZE + `TAG_SELECT_NUM_BITS + 32 + 2)) st_1e_2 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
@@ -525,17 +525,17 @@ module VX_bank
// Enqueue to CWB Queue
wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `LLFUNC_ID) && (miss_add_wb == 0)) && !((is_snp_st2 && valid_st2 && ffsq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `L2FUNC_ID) && (miss_add_wb == 0)) && !((is_snp_st2 && valid_st2 && ffsq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
wire [`WORD_SIZE_RNG] cwbq_data = readword_st2;
wire [`vx_clog2(NUMBER_REQUESTS)-1:0] cwbq_tid = miss_add_tid;
wire [4:0] cwbq_rd = miss_add_rd;
wire [1:0] cwbq_wb = miss_add_wb;
wire [`NW_M1:0] cwbq_warp_num = miss_add_warp_num;
wire [`NW_BITS-1:0] cwbq_warp_num = miss_add_warp_num;
wire [31:0] cwbq_pc = pc_st2;
wire cwbq_empty;
assign bank_wb_valid = !cwbq_empty;
VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue(
VX_generic_queue_ll #(.DATAW( `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_BITS-1+1) + `WORD_SIZE + 32 + 32), .SIZE(CWBQ_SIZE)) cwb_queue(
.clk (clk),
.reset (reset),
@@ -554,8 +554,8 @@ module VX_bank
wire[31:0] dwbq_req_addr;
wire dwbq_empty;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dwbq_req_data;
if ((FUNC_ID == `LLFUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dwbq_req_data;
if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
assign dwbq_req_data = (should_flush && dwbq_push) ? writeword_st2 : readdata_st2;
assign dwbq_req_addr = (should_flush && dwbq_push) ? (addr_st2) : ({readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK);
end else begin
@@ -603,7 +603,7 @@ module VX_bank
assign dram_fill_req_addr = addr_st2 & `BASE_ADDR_MASK;
assign dram_wb_req = !dwbq_empty;
VX_generic_queue_ll #(.DATAW( 32 + (`BANK_LINE_SIZE_WORDS * `WORD_SIZE)), .SIZE(DWBQ_SIZE)) dwb_queue(
VX_generic_queue_ll #(.DATAW( 32 + (`BANK_LINE_WORDS * `WORD_SIZE)), .SIZE(DWBQ_SIZE)) dwb_queue(
.clk (clk),
.reset (reset),

22
hw/rtl/generic_cache/VX_cache.v
View File

@@ -1,4 +1,4 @@
`include "VX_cache_config.v"
`include "VX_cache_config.vh"
module VX_cache
#(
@@ -66,7 +66,7 @@ module VX_cache
// Req meta
input wire [4:0] core_req_rd,
input wire [NUMBER_REQUESTS-1:0][1:0] core_req_wb,
input wire [`NW_M1:0] core_req_warp_num,
input wire [`NW_BITS-1:0] core_req_warp_num,
input wire [31:0] core_req_pc,
output wire delay_req,
@@ -75,7 +75,7 @@ module VX_cache
output wire [NUMBER_REQUESTS-1:0] core_wb_valid,
output wire [4:0] core_wb_req_rd,
output wire [1:0] core_wb_req_wb,
output wire [`NW_M1:0] core_wb_warp_num,
output wire [`NW_BITS-1:0] core_wb_warp_num,
output wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata,
output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_pc,
output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_address,
@@ -84,7 +84,7 @@ module VX_cache
// Dram Fill Response
input wire dram_fill_rsp,
input wire [31:0] dram_fill_rsp_addr,
input wire [`IBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
input wire [`IBANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data,
output wire dram_fill_accept,
// Dram request
@@ -93,7 +93,7 @@ module VX_cache
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [`IBANK_LINE_SIZE_RNG][31:0] dram_req_data,
output wire [`IBANK_LINE_WORDS-1:0][31:0] dram_req_data,
output wire dram_req_because_of_wb,
input wire dram_req_delay,
@@ -119,7 +119,7 @@ module VX_cache
wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_wb_tid;
wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd;
wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb;
wire [NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num;
wire [NUMBER_BANKS-1:0][`NW_BITS-1:0] per_bank_wb_warp_num;
wire [NUMBER_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data;
wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_pc;
wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_address;
@@ -134,7 +134,7 @@ module VX_cache
wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req;
wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp;
wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] per_bank_dram_wb_req_data;
wire[NUMBER_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data;
wire[NUMBER_BANKS-1:0] per_bank_reqq_full;
@@ -287,7 +287,7 @@ module VX_cache
wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] curr_bank_writedata;
wire [4:0] curr_bank_rd;
wire [NUMBER_REQUESTS-1:0][1:0] curr_bank_wb;
wire [`NW_M1:0] curr_bank_warp_num;
wire [`NW_BITS-1:0] curr_bank_warp_num;
wire [NUMBER_REQUESTS-1:0][2:0] curr_bank_mem_read;
wire [NUMBER_REQUESTS-1:0][2:0] curr_bank_mem_write;
wire [31:0] curr_bank_pc;
@@ -298,13 +298,13 @@ module VX_cache
wire [31:0] curr_bank_wb_pc;
wire [4:0] curr_bank_wb_rd;
wire [1:0] curr_bank_wb_wb;
wire [`NW_M1:0] curr_bank_wb_warp_num;
wire [`NW_BITS-1:0] curr_bank_wb_warp_num;
wire [`WORD_SIZE_RNG] curr_bank_wb_data;
wire [31:0] curr_bank_wb_address;
wire curr_bank_dram_fill_rsp;
wire [31:0] curr_bank_dram_fill_rsp_addr;
wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] curr_bank_dram_fill_rsp_data;
wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_fill_rsp_data;
wire curr_bank_dram_fill_accept;
wire curr_bank_dfqq_full;
@@ -316,7 +316,7 @@ module VX_cache
wire curr_bank_dram_wb_queue_pop;
wire curr_bank_dram_wb_req;
wire[31:0] curr_bank_dram_wb_req_addr;
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] curr_bank_dram_wb_req_data;
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_wb_req_data;
wire curr_bank_snp_req;
wire[31:0] curr_bank_snp_req_addr;

12
hw/rtl/generic_cache/VX_cache_config.v → hw/rtl/generic_cache/VX_cache_config.vh
View File

@@ -1,7 +1,7 @@
`ifndef VX_CACHE_CONFIG
`define VX_CACHE_CONFIG
`include "../VX_define.v"
`include "../VX_define.vh"
// data tid rd wb warp_num read write
@@ -10,10 +10,10 @@
`define vx_clog2(value) ((value == 1) ? 1 : $clog2(value))
`define MRVQ_METADATA_SIZE (`WORD_SIZE + `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3)
`define MRVQ_METADATA_SIZE (`WORD_SIZE + `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_BITS-1 + 1) + 3 + 3)
// 5 + 2 + 4 + 3 + 3 + 1
`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + `vx_clog2(NUMBER_REQUESTS))
`define REQ_INST_META_SIZE (5 + 2 + (`NW_BITS-1+1) + 3 + 3 + `vx_clog2(NUMBER_REQUESTS))
// `define vx_clog2_h(value, x) (value == (1 << x)) ? (x)
@@ -60,9 +60,7 @@
// 8
`define BANK_LINE_COUNT (`BANK_SIZE_BYTES/BANK_LINE_SIZE_BYTES)
// 4
`define BANK_LINE_SIZE_WORDS (BANK_LINE_SIZE_BYTES / WORD_SIZE_BYTES)
// 3:0
`define BANK_LINE_SIZE_RNG `BANK_LINE_SIZE_WORDS-1:0
`define BANK_LINE_WORDS (BANK_LINE_SIZE_BYTES / WORD_SIZE_BYTES)
// Offset is fixed
`define OFFSET_ADDR_NUM_BITS 2
@@ -73,7 +71,7 @@
`define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0
// 2
`define WORD_SELECT_NUM_BITS (`vx_clog2(`BANK_LINE_SIZE_WORDS))
`define WORD_SELECT_NUM_BITS (`vx_clog2(`BANK_LINE_WORDS))
// 2
`define WORD_SELECT_SIZE_END (`WORD_SELECT_NUM_BITS)
// 2

2
hw/rtl/generic_cache/VX_cache_core_req_bank_sel.v
View File

@@ -1,5 +1,5 @@
`include "VX_cache_config.v"
`include "VX_cache_config.vh"
module VX_cache_core_req_bank_sel
#(

2
hw/rtl/generic_cache/VX_cache_dfq_queue.v
View File

@@ -1,4 +1,4 @@
`include "VX_cache_config.v"
`include "VX_cache_config.vh"
module VX_cache_dfq_queue
#(

6
hw/rtl/generic_cache/VX_cache_dram_req_arb.v
View File

@@ -1,4 +1,4 @@
`include "VX_cache_config.v"
`include "VX_cache_config.vh"
module VX_cache_dram_req_arb
#(
@@ -62,7 +62,7 @@ module VX_cache_dram_req_arb
output wire[NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop,
input wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req,
input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr,
input wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] per_bank_dram_wb_req_data,
input wire[NUMBER_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data,
input wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp,
// real Dram request
@@ -71,7 +71,7 @@ module VX_cache_dram_req_arb
output wire dram_req_read,
output wire [31:0] dram_req_addr,
output wire [31:0] dram_req_size,
output wire [`IBANK_LINE_SIZE_RNG][31:0] dram_req_data,
output wire [`IBANK_LINE_WORDS-1:0][31:0] dram_req_data,
output wire dram_req_because_of_wb,
input wire dram_req_delay

8
hw/rtl/generic_cache/VX_cache_miss_resrv.v
View File

@@ -1,5 +1,5 @@
`include "VX_cache_config.v"
`include "VX_cache_config.vh"
module VX_cache_miss_resrv
#(
@@ -56,7 +56,7 @@ module VX_cache_miss_resrv
input wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_add_tid,
input wire[4:0] miss_add_rd,
input wire[1:0] miss_add_wb,
input wire[`NW_M1:0] miss_add_warp_num,
input wire[`NW_BITS-1:0] miss_add_warp_num,
input wire[2:0] miss_add_mem_read,
input wire[2:0] miss_add_mem_write,
input wire[31:0] miss_add_pc,
@@ -75,14 +75,14 @@ module VX_cache_miss_resrv
output wire[`vx_clog2(NUMBER_REQUESTS)-1:0] miss_resrv_tid_st0,
output wire[4:0] miss_resrv_rd_st0,
output wire[1:0] miss_resrv_wb_st0,
output wire[`NW_M1:0] miss_resrv_warp_num_st0,
output wire[`NW_BITS-1:0] miss_resrv_warp_num_st0,
output wire[2:0] miss_resrv_mem_read_st0,
output wire[31:0] miss_resrv_pc_st0,
output wire[2:0] miss_resrv_mem_write_st0
);
// Size of metadata = 32 + `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1)
// Size of metadata = 32 + `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_BITS-1 + 1)
reg[`MRVQ_METADATA_SIZE-1:0] metadata_table[MRVQ_SIZE-1:0];
reg[MRVQ_SIZE-1:0][31:0] addr_table;
reg[MRVQ_SIZE-1:0][31:0] pc_table;

14
hw/rtl/generic_cache/VX_cache_req_queue.v
View File

@@ -1,4 +1,4 @@
`include "VX_cache_config.v"
`include "VX_cache_config.vh"
module VX_cache_req_queue
#(
@@ -55,7 +55,7 @@ module VX_cache_req_queue
input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata,
input wire [4:0] bank_rd,
input wire [NUMBER_REQUESTS-1:0][1:0] bank_wb,
input wire [`NW_M1:0] bank_warp_num,
input wire [`NW_BITS-1:0] bank_warp_num,
input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_read,
input wire [NUMBER_REQUESTS-1:0][2:0] bank_mem_write,
input wire [31:0] bank_pc,
@@ -68,7 +68,7 @@ module VX_cache_req_queue
output wire [`WORD_SIZE_RNG] reqq_req_writedata_st0,
output wire [4:0] reqq_req_rd_st0,
output wire [1:0] reqq_req_wb_st0,
output wire [`NW_M1:0] reqq_req_warp_num_st0,
output wire [`NW_BITS-1:0] reqq_req_warp_num_st0,
output wire [2:0] reqq_req_mem_read_st0,
output wire [2:0] reqq_req_mem_write_st0,
output wire [31:0] reqq_req_pc_st0,
@@ -83,7 +83,7 @@ module VX_cache_req_queue
wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] out_per_writedata;
wire [4:0] out_per_rd;
wire [NUMBER_REQUESTS-1:0][1:0] out_per_wb;
wire [`NW_M1:0] out_per_warp_num;
wire [`NW_BITS-1:0] out_per_warp_num;
wire [NUMBER_REQUESTS-1:0][2:0] out_per_mem_read;
wire [NUMBER_REQUESTS-1:0][2:0] out_per_mem_write;
wire [31:0] out_per_pc;
@@ -95,7 +95,7 @@ module VX_cache_req_queue
reg [4:0] use_per_rd;
reg [NUMBER_REQUESTS-1:0][1:0] use_per_wb;
reg [31:0] use_per_pc;
reg [`NW_M1:0] use_per_warp_num;
reg [`NW_BITS-1:0] use_per_warp_num;
reg [NUMBER_REQUESTS-1:0][2:0] use_per_mem_read;
reg [NUMBER_REQUESTS-1:0][2:0] use_per_mem_write;
@@ -105,7 +105,7 @@ module VX_cache_req_queue
wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] qual_writedata;
wire [4:0] qual_rd;
wire [NUMBER_REQUESTS-1:0][1:0] qual_wb;
wire [`NW_M1:0] qual_warp_num;
wire [`NW_BITS-1:0] qual_warp_num;
wire [NUMBER_REQUESTS-1:0][2:0] qual_mem_read;
wire [NUMBER_REQUESTS-1:0][2:0] qual_mem_write;
wire [31:0] qual_pc;
@@ -120,7 +120,7 @@ module VX_cache_req_queue
wire push_qual = reqq_push && !reqq_full;
wire pop_qual = !out_empty && use_empty;
VX_generic_queue_ll #(.DATAW( (NUMBER_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUMBER_REQUESTS*2) + (`NW_M1+1) + (NUMBER_REQUESTS * (3 + 3)) + 32 ), .SIZE(REQQ_SIZE)) reqq_queue(
VX_generic_queue_ll #(.DATAW( (NUMBER_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUMBER_REQUESTS*2) + (`NW_BITS-1+1) + (NUMBER_REQUESTS * (3 + 3)) + 32 ), .SIZE(REQQ_SIZE)) reqq_queue(
.clk (clk),
.reset (reset),
.push (push_qual),

8
hw/rtl/generic_cache/VX_cache_wb_sel_merge.v
View File

@@ -1,4 +1,4 @@
`include "VX_cache_config.v"
`include "VX_cache_config.vh"
module VX_cache_wb_sel_merge
#(
@@ -53,7 +53,7 @@ module VX_cache_wb_sel_merge
input wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_wb_tid,
input wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd,
input wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb,
input wire [NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num,
input wire [NUMBER_BANKS-1:0][`NW_BITS-1:0] per_bank_wb_warp_num,
input wire [NUMBER_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data,
input wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_pc,
input wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_address,
@@ -67,7 +67,7 @@ module VX_cache_wb_sel_merge
output reg [NUMBER_REQUESTS-1:0][31:0] core_wb_pc,
output wire [4:0] core_wb_req_rd,
output wire [1:0] core_wb_req_wb,
output wire [`NW_M1:0] core_wb_warp_num,
output wire [`NW_BITS-1:0] core_wb_warp_num,
output reg [NUMBER_REQUESTS-1:0][31:0] core_wb_address
);
@@ -105,7 +105,7 @@ module VX_cache_wb_sel_merge
core_wb_pc = 0;
core_wb_address = 0;
for (this_bank = 0; this_bank < NUMBER_BANKS; this_bank = this_bank + 1) begin
if ((FUNC_ID == `LLFUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
if (found_bank && !core_wb_valid[per_bank_wb_tid[this_bank]] && per_bank_wb_valid[this_bank] && ((this_bank == main_bank_index) || (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))) begin
core_wb_valid[per_bank_wb_tid[this_bank]] = 1;

6
hw/rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v
View File

@@ -1,4 +1,4 @@
`include "VX_cache_config.v"
`include "VX_cache_config.vh"
module VX_dcache_llv_resp_bank_sel
#(
@@ -48,13 +48,13 @@ module VX_dcache_llv_resp_bank_sel
output reg [NUMBER_BANKS-1:0] per_bank_llvq_pop,
input wire[NUMBER_BANKS-1:0] per_bank_llvq_valid,
input wire[NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr,
input wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data,
input wire[NUMBER_BANKS-1:0][`BANK_LINE_WORDS-1:0][31:0] per_bank_llvq_res_data,
input wire[NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid,
input wire llvq_pop,
output reg[NUMBER_REQUESTS-1:0] llvq_valid,
output reg[NUMBER_REQUESTS-1:0][31:0] llvq_res_addr,
output reg[NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data
output reg[NUMBER_REQUESTS-1:0][`BANK_LINE_WORDS-1:0][31:0] llvq_res_data
);

2
hw/rtl/generic_cache/VX_fill_invalidator.v
View File

@@ -1,4 +1,4 @@
`include "VX_cache_config.v"
`include "VX_cache_config.vh"
module VX_fill_invalidator
#(

2
hw/rtl/generic_cache/VX_prefetcher.v
View File

@@ -1,4 +1,4 @@
`include "VX_cache_config.v"
`include "VX_cache_config.vh"
module VX_prefetcher
#(

2
hw/rtl/generic_cache/VX_snp_fwd_arb.v
View File

@@ -1,4 +1,4 @@
`include "VX_cache_config.v"
`include "VX_cache_config.vh"
module VX_snp_fwd_arb
#(

40
hw/rtl/generic_cache/VX_tag_data_access.v
View File

@@ -1,4 +1,4 @@
`include "VX_cache_config.v"
`include "VX_cache_config.vh"
module VX_tag_data_access
#(
@@ -60,12 +60,12 @@ module VX_tag_data_access
input wire writefill_st1e,
input wire[31:0] writeaddr_st1e,
input wire[`WORD_SIZE_RNG] writeword_st1e,
input wire[`DBANK_LINE_SIZE_RNG][31:0] writedata_st1e,
input wire[`DBANK_LINE_WORDS-1:0][31:0] writedata_st1e,
input wire[2:0] mem_write_st1e,
input wire[2:0] mem_read_st1e,
output wire[`WORD_SIZE_RNG] readword_st1e,
output wire[`DBANK_LINE_SIZE_RNG][31:0] readdata_st1e,
output wire[`DBANK_LINE_WORDS-1:0][31:0] readdata_st1e,
output wire[`TAG_SELECT_SIZE_RNG] readtag_st1e,
output wire miss_st1e,
output wire dirty_st1e,
@@ -74,25 +74,25 @@ module VX_tag_data_access
);
reg[`DBANK_LINE_SIZE_RNG][31:0] readdata_st[STAGE_1_CYCLES-1:0];
reg[`DBANK_LINE_WORDS-1:0][31:0] readdata_st[STAGE_1_CYCLES-1:0];
reg read_valid_st1c[STAGE_1_CYCLES-1:0];
reg read_dirty_st1c[STAGE_1_CYCLES-1:0];
reg[`TAG_SELECT_SIZE_RNG] read_tag_st1c [STAGE_1_CYCLES-1:0];
reg[`DBANK_LINE_SIZE_RNG][31:0] read_data_st1c [STAGE_1_CYCLES-1:0];
reg[`DBANK_LINE_WORDS-1:0][31:0] read_data_st1c [STAGE_1_CYCLES-1:0];
wire qual_read_valid_st1;
wire qual_read_dirty_st1;
wire[`TAG_SELECT_SIZE_RNG] qual_read_tag_st1;
wire[`DBANK_LINE_SIZE_RNG][31:0] qual_read_data_st1;
wire[`DBANK_LINE_WORDS-1:0][31:0] qual_read_data_st1;
wire use_read_valid_st1e;
wire use_read_dirty_st1e;
wire[`TAG_SELECT_SIZE_RNG] use_read_tag_st1e;
wire[`DBANK_LINE_SIZE_RNG][31:0] use_read_data_st1e;
wire[`DBANK_LINE_SIZE_RNG][3:0] use_write_enable;
wire[`DBANK_LINE_SIZE_RNG][31:0] use_write_data;
wire[`DBANK_LINE_WORDS-1:0][31:0] use_read_data_st1e;
wire[`DBANK_LINE_WORDS-1:0][3:0] use_write_enable;
wire[`DBANK_LINE_WORDS-1:0][31:0] use_write_data;
wire sw, sb, sh;
@@ -140,8 +140,8 @@ module VX_tag_data_access
.fill_sent (fill_sent)
);
// VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_SIZE_WORDS*32) )) s0_1_c0 (
VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_SIZE_WORDS*32) ), .Valid(0)) s0_1_c0 (
// VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_WORDS*32) )) s0_1_c0 (
VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_WORDS*32) ), .Valid(0)) s0_1_c0 (
.clk (clk),
.reset(reset),
.stall(stall),
@@ -153,7 +153,7 @@ module VX_tag_data_access
genvar curr_stage;
generate
for (curr_stage = 1; curr_stage < STAGE_1_CYCLES-1; curr_stage = curr_stage + 1) begin
VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_SIZE_WORDS*32) )) s0_1_cc (
VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_NUM_BITS + (`DBANK_LINE_WORDS*32) )) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall),
@@ -170,7 +170,7 @@ module VX_tag_data_access
assign use_read_tag_st1e = (FUNC_ID == `SFUNC_ID) ? writeaddr_st1e[`TAG_SELECT_ADDR_RNG] : read_tag_st1c [STAGE_1_CYCLES-1]; // Tag is always the same in SM
genvar curr_w;
for (curr_w = 0; curr_w < `DBANK_LINE_SIZE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-1][curr_w][31:0];
for (curr_w = 0; curr_w < `DBANK_LINE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-1][curr_w][31:0];
// assign use_read_data_st1e = read_data_st1c [STAGE_1_CYCLES-1];
/////////////////////// LOAD LOGIC ///////////////////
@@ -243,23 +243,23 @@ module VX_tag_data_access
wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e && !is_snp_st1e;
wire force_write = real_writefill;
wire[`DBANK_LINE_SIZE_RNG][3:0] we;
wire[`DBANK_LINE_SIZE_RNG][31:0] data_write;
wire[`DBANK_LINE_WORDS-1:0][3:0] we;
wire[`DBANK_LINE_WORDS-1:0][31:0] data_write;
genvar g;
generate
for (g = 0; g < `DBANK_LINE_SIZE_WORDS; g = g + 1) begin : write_enables
for (g = 0; g < `DBANK_LINE_WORDS; g = g + 1) begin : write_enables
wire normal_write = (block_offset == g[`WORD_SELECT_SIZE_RNG]) && should_write && !real_writefill;
assign we[g] = (force_write) ? 4'b1111 :
(should_write && !real_writefill && (FUNC_ID == `LLFUNC_ID)) ? 4'b1111 :
(should_write && !real_writefill && (FUNC_ID == `L2FUNC_ID)) ? 4'b1111 :
(normal_write && sw) ? 4'b1111 :
(normal_write && sb) ? sb_mask :
(normal_write && sh) ? sh_mask :
4'b0000;
if (!(FUNC_ID == `LLFUNC_ID)) assign data_write[g] = force_write ? writedata_st1e[g] : use_write_dat;
if (!(FUNC_ID == `L2FUNC_ID)) assign data_write[g] = force_write ? writedata_st1e[g] : use_write_dat;
end
if ((FUNC_ID == `LLFUNC_ID)) begin
if ((FUNC_ID == `L2FUNC_ID)) begin
assign data_write = force_write ? writedata_st1e : writeword_st1e;
end
endgenerate
@@ -268,7 +268,7 @@ module VX_tag_data_access
assign use_write_data = data_write;
///////////////////////
if (FUNC_ID == `LLFUNC_ID) begin
if (FUNC_ID == `L2FUNC_ID) begin
assign readword_st1e = read_data_st1c[STAGE_1_CYCLES-1];
end else begin
assign readword_st1e = data_Qual;

12
hw/rtl/generic_cache/VX_tag_data_structure.v
View File

@@ -1,4 +1,4 @@
`include "VX_cache_config.v"
`include "VX_cache_config.vh"
module VX_tag_data_structure
#(
@@ -55,18 +55,18 @@ module VX_tag_data_structure
output wire read_valid,
output wire read_dirty,
output wire[`TAG_SELECT_SIZE_RNG] read_tag,
output wire[`DBANK_LINE_SIZE_RNG][31:0] read_data,
output wire[`DBANK_LINE_WORDS-1:0][31:0] read_data,
input wire invalidate,
input wire[`DBANK_LINE_SIZE_RNG][3:0] write_enable,
input wire[`DBANK_LINE_WORDS-1:0][3:0] write_enable,
input wire write_fill,
input wire[31:0] write_addr,
input wire[`DBANK_LINE_SIZE_RNG][31:0] write_data,
input wire[`DBANK_LINE_WORDS-1:0][31:0] write_data,
input wire fill_sent
);
reg[`DBANK_LINE_SIZE_RNG][3:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg[`DBANK_LINE_WORDS-1:0][3:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg[`TAG_SELECT_SIZE_RNG] tag [`BANK_LINE_COUNT-1:0];
reg valid[`BANK_LINE_COUNT-1:0];
reg dirty[`BANK_LINE_COUNT-1:0];
@@ -110,7 +110,7 @@ module VX_tag_data_structure
valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0;
end
for (f = 0; f < `DBANK_LINE_SIZE_WORDS; f = f + 1) begin
for (f = 0; f < `DBANK_LINE_WORDS; f = f + 1) begin
if (write_enable[f][0]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][0] <= write_data[f][7 :0 ];
if (write_enable[f][1]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][1] <= write_data[f][15:8 ];
if (write_enable[f][2]) data[write_addr[`LINE_SELECT_ADDR_RNG]][f][2] <= write_data[f][23:16];