added config.vh
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4
hw/rtl/cache/cache_set.v
vendored
4
hw/rtl/cache/cache_set.v
vendored
@@ -2,7 +2,7 @@
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// Also add a bit about wheter the "Way ID" is valid / being held or if it is just default
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// Also make sure all possible output states are transmitted back to the bank correctly
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// `include "VX_define.v"
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// `include "VX_define.vh"
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module cache_set(clk,
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rst,
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// These next 4 are possible modes that the Set could be in, I am making them 4 different variables for indexing purposes
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@@ -94,7 +94,7 @@ module cache_set(clk,
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readdata <= data[3];
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end
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end else if (access) begin
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//tag[`NT_M1:0] <= i_p_addr[`NT_M1:0][13:12];
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//tag[`NUM_THREADS-1:0] <= i_p_addr[`NUM_THREADS-1:0][13:12];
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counter <= ((counter + 1) ^ 3'b100); // Counter determining which to evict in the event of miss only increment when miss !!! NEED TO FIX LOGIC
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// Hit in First Column
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if (tag[0] == o_tag && valid[0]) begin
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