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added config.vh

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This commit is contained in:
Blaise Tine
2020-04-16 07:49:19 -04:00
parent c913e542e9
commit 81745f08c9
109 changed files with 1426 additions and 1544 deletions
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4
hw/rtl/cache/VX_Cache_Bank.v vendored
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@@ -2,7 +2,7 @@
// Also add a bit about wheter the "Way ID" is valid / being held or if it is just default
// Also make sure all possible output states are transmitted back to the bank correctly
`include "VX_define.v"
`include "VX_define.vh"
module VX_Cache_Bank
#(
@@ -67,7 +67,7 @@ module VX_Cache_Bank
localparam RECIV_MEM_RSP = 2;
localparam BLOCK_NUM_BITS = `CLOG2(CACHE_BLOCK);
localparam BLOCK_NUM_BITS = `LOG2UP(CACHE_BLOCK);
// Inputs
input wire rst;
input wire clk;

2
hw/rtl/cache/VX_cache_bank_valid.v vendored
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@@ -1,4 +1,4 @@
`include "VX_define.v"
`include "VX_define.vh"
module VX_cache_bank_valid
#(

2
hw/rtl/cache/VX_cache_data.v vendored
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@@ -1,4 +1,4 @@
`include "VX_define.v"
`include "VX_define.vh"
module VX_cache_data
#(

2
hw/rtl/cache/VX_cache_data_per_index.v vendored
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@@ -1,4 +1,4 @@
`include "VX_define.v"
`include "VX_define.vh"
module VX_cache_data_per_index
#(

2
hw/rtl/cache/VX_d_cache.v vendored
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@@ -8,7 +8,7 @@
// TO DO:
// - Send in a response from memory of what the data is from the test bench
`include "VX_define.v"
`include "VX_define.vh"
//`include "VX_Cache_Bank.v"
//`include "VX_cache_bank_valid.v"
//`include "VX_priority_encoder.v"

24
hw/rtl/cache/VX_d_cache_encapsulate.v vendored
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@@ -1,4 +1,4 @@
`include "VX_define.v"
`include "VX_define.vh"
`define NUM_WORDS_PER_BLOCK 4
@@ -33,17 +33,17 @@ module VX_d_cache_encapsulate (
//parameter cache_entry = 9;
input wire clk, rst;
input wire i_p_valid[`NT_M1:0];
input wire [31:0] i_p_addr[`NT_M1:0];
input wire i_p_valid[`NUM_THREADS-1:0];
input wire [31:0] i_p_addr[`NUM_THREADS-1:0];
input wire i_p_initial_request;
input wire [31:0] i_p_writedata[`NT_M1:0];
input wire [31:0] i_p_writedata[`NUM_THREADS-1:0];
input wire i_p_read_or_write;
input wire [31:0] i_m_readdata[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0];
input wire i_m_ready;
output reg [31:0] o_p_readdata[`NT_M1:0];
output reg o_p_readdata_valid[`NT_M1:0] ;
output reg [31:0] o_p_readdata[`NUM_THREADS-1:0];
output reg o_p_readdata_valid[`NUM_THREADS-1:0] ;
output reg o_p_waitrequest;
output reg [31:0] o_m_addr;
@@ -53,12 +53,12 @@ module VX_d_cache_encapsulate (
// Inter
wire [`NT_M1:0] i_p_valid_inter;
wire [`NT_M1:0][31:0] i_p_addr_inter;
wire [`NT_M1:0][31:0] i_p_writedata_inter;
wire [`NUM_THREADS-1:0] i_p_valid_inter;
wire [`NUM_THREADS-1:0][31:0] i_p_addr_inter;
wire [`NUM_THREADS-1:0][31:0] i_p_writedata_inter;
reg [`NT_M1:0][31:0] o_p_readdata_inter;
reg [`NT_M1:0] o_p_readdata_valid_inter;
reg [`NUM_THREADS-1:0][31:0] o_p_readdata_inter;
reg [`NUM_THREADS-1:0] o_p_readdata_valid_inter;
reg[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata_inter;
wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_inter;
@@ -66,7 +66,7 @@ module VX_d_cache_encapsulate (
genvar curr_thraed, curr_bank, curr_word;
generate
for (curr_thraed = 0; curr_thraed < `NT; curr_thraed = curr_thraed + 1) begin : threads
for (curr_thraed = 0; curr_thraed < `NUM_THREADS; curr_thraed = curr_thraed + 1) begin : threads
assign i_p_valid_inter[curr_thraed] = i_p_valid[curr_thraed];
assign i_p_addr_inter[curr_thraed] = i_p_addr[curr_thraed];
assign i_p_writedata_inter[curr_thraed] = i_p_writedata[curr_thraed];

12
hw/rtl/cache/VX_d_cache_tb.v vendored
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@@ -1,4 +1,4 @@
`include "VX_define.v"
`include "VX_define.vh"
`include "VX_d_cache.v"
module VX_d_cache_tb;
@@ -6,13 +6,13 @@ module VX_d_cache_tb;
parameter NUMBER_BANKS = 8;
reg clk, reset, im_ready;
reg [`NT_M1:0] i_p_valid;
reg [`NT_M1:0][13:0] i_p_addr; // FIXME
reg [`NUM_THREADS-1:0] i_p_valid;
reg [`NUM_THREADS-1:0][13:0] i_p_addr; // FIXME
reg i_p_initial_request;
reg [`NT_M1:0][31:0] i_p_writedata;
reg [`NUM_THREADS-1:0][31:0] i_p_writedata;
reg i_p_read_or_write; //, i_p_write;
reg [`NT_M1:0][31:0] o_p_readdata;
reg [`NT_M1:0] o_p_readdata_valid;
reg [`NUM_THREADS-1:0][31:0] o_p_readdata;
reg [`NUM_THREADS-1:0] o_p_readdata_valid;
reg o_p_waitrequest;
reg [13:0] o_m_addr; // Only one address is sent out at a time to memory
reg o_m_valid;

4
hw/rtl/cache/cache_set.v vendored
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@@ -2,7 +2,7 @@
// Also add a bit about wheter the "Way ID" is valid / being held or if it is just default
// Also make sure all possible output states are transmitted back to the bank correctly
// `include "VX_define.v"
// `include "VX_define.vh"
module cache_set(clk,
rst,
// These next 4 are possible modes that the Set could be in, I am making them 4 different variables for indexing purposes
@@ -94,7 +94,7 @@ module cache_set(clk,
readdata <= data[3];
end
end else if (access) begin
//tag[`NT_M1:0] <= i_p_addr[`NT_M1:0][13:12];
//tag[`NUM_THREADS-1:0] <= i_p_addr[`NUM_THREADS-1:0][13:12];
counter <= ((counter + 1) ^ 3'b100); // Counter determining which to evict in the event of miss only increment when miss !!! NEED TO FIX LOGIC
// Hit in First Column
if (tag[0] == o_tag && valid[0]) begin