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added config.vh

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This commit is contained in:
Blaise Tine
2020-04-16 07:49:19 -04:00
parent c913e542e9
commit 81745f08c9
109 changed files with 1426 additions and 1544 deletions
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244
hw/rtl/Vortex_Cluster.v
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@@ -1,20 +1,18 @@
`include "VX_define.v"
`include "VX_cache_config.v"
`include "VX_define.vh"
`include "VX_cache_config.vh"
module Vortex_Cluster
#(
parameter CLUSTER_ID = 0
)
(
#(
parameter CLUSTER_ID = 0
) (
// Clock
input wire clk,
input wire reset,
// IO
output wire[`NUMBER_CORES_PER_CLUSTER-1:0] io_valid,
output wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] io_data,
output wire[`NUM_CORES_PER_CLUSTER-1:0] io_valid,
output wire[`NUM_CORES_PER_CLUSTER-1:0][31:0] io_data,
// DRAM Req
output wire out_dram_req,
@@ -22,7 +20,7 @@ module Vortex_Cluster
output wire out_dram_req_read,
output wire [31:0] out_dram_req_addr,
output wire [31:0] out_dram_req_size,
output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG],
output wire [31:0] out_dram_req_data[`DBANK_LINE_WORDS-1:0],
output wire [31:0] out_dram_expected_lat,
input wire out_dram_req_delay,
@@ -30,8 +28,7 @@ module Vortex_Cluster
output wire out_dram_fill_accept,
input wire out_dram_fill_rsp,
input wire [31:0] out_dram_fill_rsp_addr,
input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_WORDS-1:0],
// LLC Snooping
input wire llc_snp_req,
@@ -40,142 +37,133 @@ module Vortex_Cluster
output wire out_ebreak
);
// DRAM Dcache Req
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_write;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_read;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_addr;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_size;
wire[`NUMBER_CORES_PER_CLUSTER-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_req_data;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_expected_lat;
wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_req;
wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_req_write;
wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_req_read;
wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_addr;
wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_req_size;
wire[`NUM_CORES_PER_CLUSTER-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_req_data;
wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_expected_lat;
// DRAM Dcache Res
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_fill_accept;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_fill_rsp;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_fill_rsp_addr;
wire[`NUMBER_CORES_PER_CLUSTER-1:0][`DBANK_LINE_SIZE_RNG][31:0] per_core_dram_fill_rsp_data;
wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_fill_accept;
wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_dram_fill_rsp;
wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_dram_fill_rsp_addr;
wire[`NUM_CORES_PER_CLUSTER-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_dram_fill_rsp_data;
// DRAM Icache Req
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_write;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_read;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_addr;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_size;
wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_req_data;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_expected_lat;
wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req;
wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_write;
wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_req_read;
wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_addr;
wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_req_size;
wire[`NUM_CORES_PER_CLUSTER-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_req_data;
wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_expected_lat;
// DRAM Icache Res
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_accept;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_rsp;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_fill_rsp_addr;
wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_fill_rsp_data;
wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_accept;
wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_I_dram_fill_rsp;
wire[`NUM_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_fill_rsp_addr;
wire[`NUM_CORES_PER_CLUSTER-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_fill_rsp_data;
// Out ebreak
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_out_ebreak;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_io_valid;
wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_io_data;
wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_out_ebreak;
wire[`NUM_CORES_PER_CLUSTER-1:0] per_core_io_valid;
wire[`NUM_CORES_PER_CLUSTER-1:0][31:0] per_core_io_data;
wire l2c_core_accept;
wire snp_fwd;
wire[31:0] snp_fwd_addr;
wire[`NUMBER_CORES_PER_CLUSTER-1:0] snp_fwd_delay;
wire snp_fwd;
wire[31:0] snp_fwd_addr;
wire[`NUM_CORES_PER_CLUSTER-1:0] snp_fwd_delay;
assign out_ebreak = (&per_core_out_ebreak);
genvar curr_core;
generate
for (curr_core = 0; curr_core < `NUMBER_CORES_PER_CLUSTER; curr_core=curr_core+1) begin
for (curr_core = 0; curr_core < `NUM_CORES_PER_CLUSTER; curr_core=curr_core+1) begin
wire [`IBANK_LINE_SIZE_RNG][31:0] curr_core_I_dram_req_data;
wire [`DBANK_LINE_SIZE_RNG][31:0] curr_core_dram_req_data ;
wire [`IBANK_LINE_WORDS-1:0][31:0] curr_core_I_dram_req_data;
wire [`DBANK_LINE_WORDS-1:0][31:0] curr_core_dram_req_data ;
assign io_valid[curr_core] = per_core_io_valid[curr_core];
assign io_data [curr_core] = per_core_io_data [curr_core];
Vortex #(.CORE_ID(curr_core + (CLUSTER_ID * `NUMBER_CORES_PER_CLUSTER))) vortex_core(
.clk (clk),
.reset (reset),
.io_valid (per_core_io_valid [curr_core]),
.io_data (per_core_io_data [curr_core]),
.dram_req (per_core_dram_req [curr_core]),
.dram_req_write (per_core_dram_req_write [curr_core]),
.dram_req_read (per_core_dram_req_read [curr_core]),
.dram_req_addr (per_core_dram_req_addr [curr_core]),
.dram_req_size (per_core_dram_req_size [curr_core]),
.dram_req_data (curr_core_dram_req_data ),
.dram_expected_lat (per_core_dram_expected_lat [curr_core]),
.dram_fill_accept (per_core_dram_fill_accept [curr_core]),
.dram_fill_rsp (per_core_dram_fill_rsp [curr_core]),
.dram_fill_rsp_addr (per_core_dram_fill_rsp_addr [curr_core]),
.dram_fill_rsp_data (per_core_dram_fill_rsp_data [curr_core]),
.I_dram_req (per_core_I_dram_req [curr_core]),
.I_dram_req_write (per_core_I_dram_req_write [curr_core]),
.I_dram_req_read (per_core_I_dram_req_read [curr_core]),
.I_dram_req_addr (per_core_I_dram_req_addr [curr_core]),
.I_dram_req_size (per_core_I_dram_req_size [curr_core]),
.I_dram_req_data (curr_core_I_dram_req_data ),
.I_dram_expected_lat (per_core_I_dram_expected_lat [curr_core]),
.I_dram_fill_accept (per_core_I_dram_fill_accept [curr_core]),
.I_dram_fill_rsp (per_core_I_dram_fill_rsp [curr_core]),
.I_dram_fill_rsp_addr (per_core_I_dram_fill_rsp_addr[curr_core]),
.I_dram_fill_rsp_data (per_core_I_dram_fill_rsp_data[curr_core]),
.dram_req_delay (l2c_core_accept ),
.out_ebreak (per_core_out_ebreak [curr_core]),
.snp_req (snp_fwd),
.snp_req_addr (snp_fwd_addr),
.snp_req_delay (snp_fwd_delay[curr_core]),
.I_snp_req (0),
.I_snp_req_addr (),
.I_snp_req_delay ()
);
Vortex #(
.CORE_ID(curr_core + (CLUSTER_ID * `NUM_CORES_PER_CLUSTER))
) vortex_core(
.clk (clk),
.reset (reset),
.io_valid (per_core_io_valid [curr_core]),
.io_data (per_core_io_data [curr_core]),
.dram_req (per_core_dram_req [curr_core]),
.dram_req_write (per_core_dram_req_write [curr_core]),
.dram_req_read (per_core_dram_req_read [curr_core]),
.dram_req_addr (per_core_dram_req_addr [curr_core]),
.dram_req_size (per_core_dram_req_size [curr_core]),
.dram_req_data (curr_core_dram_req_data ),
.dram_expected_lat (per_core_dram_expected_lat [curr_core]),
.dram_fill_accept (per_core_dram_fill_accept [curr_core]),
.dram_fill_rsp (per_core_dram_fill_rsp [curr_core]),
.dram_fill_rsp_addr (per_core_dram_fill_rsp_addr [curr_core]),
.dram_fill_rsp_data (per_core_dram_fill_rsp_data [curr_core]),
.I_dram_req (per_core_I_dram_req [curr_core]),
.I_dram_req_write (per_core_I_dram_req_write [curr_core]),
.I_dram_req_read (per_core_I_dram_req_read [curr_core]),
.I_dram_req_addr (per_core_I_dram_req_addr [curr_core]),
.I_dram_req_size (per_core_I_dram_req_size [curr_core]),
.I_dram_req_data (curr_core_I_dram_req_data ),
.I_dram_expected_lat (per_core_I_dram_expected_lat [curr_core]),
.I_dram_fill_accept (per_core_I_dram_fill_accept [curr_core]),
.I_dram_fill_rsp (per_core_I_dram_fill_rsp [curr_core]),
.I_dram_fill_rsp_addr (per_core_I_dram_fill_rsp_addr[curr_core]),
.I_dram_fill_rsp_data (per_core_I_dram_fill_rsp_data[curr_core]),
.dram_req_delay (l2c_core_accept ),
.out_ebreak (per_core_out_ebreak [curr_core]),
.snp_req (snp_fwd),
.snp_req_addr (snp_fwd_addr),
.snp_req_delay (snp_fwd_delay[curr_core]),
.I_snp_req (0),
.I_snp_req_addr (),
.I_snp_req_delay ()
);
assign per_core_dram_req_data [curr_core] = curr_core_dram_req_data;
assign per_core_I_dram_req_data[curr_core] = curr_core_I_dram_req_data;
end
endgenerate
//////////////////// L2 Cache ////////////////////
wire[`LLNUMBER_REQUESTS-1:0] l2c_core_req;
wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_write;
wire[`LLNUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_read;
wire[`LLNUMBER_REQUESTS-1:0][31:0] l2c_core_req_addr;
wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_core_req_data;
wire[`LLNUMBER_REQUESTS-1:0][1:0] l2c_core_req_wb;
wire[`L2NUMBER_REQUESTS-1:0] l2c_core_req;
wire[`L2NUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_write;
wire[`L2NUMBER_REQUESTS-1:0][2:0] l2c_core_req_mem_read;
wire[`L2NUMBER_REQUESTS-1:0][31:0] l2c_core_req_addr;
wire[`L2NUMBER_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_core_req_data;
wire[`L2NUMBER_REQUESTS-1:0][1:0] l2c_core_req_wb;
wire[`LLNUMBER_REQUESTS-1:0] l2c_core_no_wb_slot;
wire[`L2NUMBER_REQUESTS-1:0] l2c_core_no_wb_slot;
wire[`L2NUMBER_REQUESTS-1:0] l2c_wb;
wire[`L2NUMBER_REQUESTS-1:0] [31:0] l2c_wb_addr;
wire[`L2NUMBER_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_wb_data;
wire[`LLNUMBER_REQUESTS-1:0] l2c_wb;
wire[`LLNUMBER_REQUESTS-1:0] [31:0] l2c_wb_addr;
wire[`LLNUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l2c_wb_data;
wire[`DBANK_LINE_SIZE_RNG][31:0] dram_req_data_port;
wire[`DBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data_port;
wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port;
wire[`DBANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data_port;
genvar llb_index;
generate
for (llb_index = 0; llb_index < `DBANK_LINE_SIZE_WORDS; llb_index=llb_index+1) begin
for (llb_index = 0; llb_index < `DBANK_LINE_WORDS; llb_index=llb_index+1) begin
assign out_dram_req_data [llb_index] = dram_req_data_port[llb_index];
assign dram_fill_rsp_data_port[llb_index] = out_dram_fill_rsp_data[llb_index];
end
endgenerate
//
genvar l2c_curr_core;
generate
for (l2c_curr_core = 0; l2c_curr_core < `LLNUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin
for (l2c_curr_core = 0; l2c_curr_core < `L2NUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin
// Core Request
assign l2c_core_req [l2c_curr_core] = per_core_dram_req [(l2c_curr_core/2)];
assign l2c_core_req [l2c_curr_core+1] = per_core_I_dram_req[(l2c_curr_core/2)];
@@ -214,29 +202,27 @@ module Vortex_Cluster
wire dram_snp_full;
wire dram_req_because_of_wb;
VX_cache #(
.CACHE_SIZE_BYTES (`LLCACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (`LLBANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (`LLNUMBER_BANKS),
.WORD_SIZE_BYTES (`LLWORD_SIZE_BYTES),
.NUMBER_REQUESTS (`LLNUMBER_REQUESTS),
.STAGE_1_CYCLES (`LLSTAGE_1_CYCLES),
.FUNC_ID (`LLFUNC_ID),
.REQQ_SIZE (`LLREQQ_SIZE),
.MRVQ_SIZE (`LLMRVQ_SIZE),
.DFPQ_SIZE (`LLDFPQ_SIZE),
.SNRQ_SIZE (`LLSNRQ_SIZE),
.CWBQ_SIZE (`LLCWBQ_SIZE),
.DWBQ_SIZE (`LLDWBQ_SIZE),
.DFQQ_SIZE (`LLDFQQ_SIZE),
.LLVQ_SIZE (`LLLLVQ_SIZE),
.FFSQ_SIZE (`LLFFSQ_SIZE),
.PRFQ_SIZE (`LLPRFQ_SIZE),
.PRFQ_STRIDE (`LLPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`LLFILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`LLSIMULATED_DRAM_LATENCY_CYCLES)
)
gpu_l2cache
(
.CACHE_SIZE_BYTES (`L2CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (`L2BANK_LINE_SIZE_BYTES),
.NUMBER_BANKS (`L2NUMBER_BANKS),
.WORD_SIZE_BYTES (`L2WORD_SIZE_BYTES),
.NUMBER_REQUESTS (`L2NUMBER_REQUESTS),
.STAGE_1_CYCLES (`L2STAGE_1_CYCLES),
.FUNC_ID (`L2FUNC_ID),
.REQQ_SIZE (`L2REQQ_SIZE),
.MRVQ_SIZE (`L2MRVQ_SIZE),
.DFPQ_SIZE (`L2DFPQ_SIZE),
.SNRQ_SIZE (`L2SNRQ_SIZE),
.CWBQ_SIZE (`L2CWBQ_SIZE),
.DWBQ_SIZE (`L2DWBQ_SIZE),
.DFQQ_SIZE (`L2DFQQ_SIZE),
.LLVQ_SIZE (`L2LLVQ_SIZE),
.FFSQ_SIZE (`L2FFSQ_SIZE),
.PRFQ_SIZE (`L2PRFQ_SIZE),
.PRFQ_STRIDE (`L2PRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`L2FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`L2SIMULATED_DRAM_LATENCY_CYCLES)
) gpu_l2cache (
.clk (clk),
.reset (reset),
@@ -295,8 +281,6 @@ module Vortex_Cluster
.snp_fwd (snp_fwd),
.snp_fwd_addr (snp_fwd_addr),
.snp_fwd_delay (|snp_fwd_delay)
);
);
endmodule