added config.vh
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@@ -1,4 +1,4 @@
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`include "VX_define.v"
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`include "VX_define.vh"
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module VX_csr_pipe
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#(
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@@ -14,8 +14,8 @@ module VX_csr_pipe
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output wire stall_gpr_csr
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);
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wire[`NT_M1:0] valid_s2;
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wire[`NW_M1:0] warp_num_s2;
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wire[`NUM_THREADS-1:0] valid_s2;
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wire[`NW_BITS-1:0] warp_num_s2;
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wire[4:0] rd_s2;
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wire[1:0] wb_s2;
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wire[4:0] alu_op_s2;
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@@ -60,7 +60,7 @@ module VX_csr_pipe
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wire zero = 0;
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VX_generic_register #(.N(32 + 32 + 12 + 1 + 2 + 5 + (`NW_M1+1) + `NT)) csr_reg_s2 (
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VX_generic_register #(.N(32 + 32 + 12 + 1 + 2 + 5 + (`NW_BITS-1+1) + `NUM_THREADS)) csr_reg_s2 (
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.clk (clk),
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.reset(reset),
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.stall(no_slot_csr),
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@@ -70,28 +70,26 @@ module VX_csr_pipe
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);
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wire[`NT_M1:0][31:0] final_csr_data;
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wire[`NUM_THREADS-1:0][31:0] final_csr_data;
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wire[`NT_M1:0][31:0] thread_ids;
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wire[`NT_M1:0][31:0] warp_ids;
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wire[`NT_M1:0][31:0] warp_idz;
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wire[`NT_M1:0][31:0] csr_vec_read_data_s2;
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wire[`NUM_THREADS-1:0][31:0] thread_ids;
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wire[`NUM_THREADS-1:0][31:0] warp_ids;
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wire[`NUM_THREADS-1:0][31:0] warp_idz;
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wire[`NUM_THREADS-1:0][31:0] csr_vec_read_data_s2;
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genvar cur_t;
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for (cur_t = 0; cur_t < `NT; cur_t = cur_t + 1) begin
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for (cur_t = 0; cur_t < `NUM_THREADS; cur_t = cur_t + 1) begin
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assign thread_ids[cur_t] = cur_t;
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end
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genvar cur_tw;
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for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin
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assign warp_ids[cur_tw] = {{(31-`NW_M1){1'b0}}, warp_num_s2};
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assign warp_idz[cur_tw] = (warp_num_s2 + (CORE_ID*`NW));
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for (cur_tw = 0; cur_tw < `NUM_THREADS; cur_tw = cur_tw + 1) begin
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assign warp_ids[cur_tw] = warp_num_s2;
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assign warp_idz[cur_tw] = 32'(warp_num_s2 + (CORE_ID * `NUM_WARPS));
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end
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genvar cur_v;
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for (cur_v = 0; cur_v < `NT; cur_v = cur_v + 1) begin
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for (cur_v = 0; cur_v < `NUM_THREADS; cur_v = cur_v + 1) begin
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assign csr_vec_read_data_s2[cur_v] = csr_read_data_s2;
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end
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@@ -104,7 +102,6 @@ module VX_csr_pipe
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warp_id_select ? warp_idz :
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csr_vec_read_data_s2;
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assign VX_csr_wb.valid = valid_s2;
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assign VX_csr_wb.warp_num = warp_num_s2;
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assign VX_csr_wb.rd = rd_s2;
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