Before fixing miss rsrv for ST->LD sequences

2020-03-03 16:57:05 -08:00
parent 361fc2c3fe
commit 80af320fdb
6 changed files with 110 additions and 20 deletions
--- a/rtl/VX_cache/VX_cache.v
+++ b/rtl/VX_cache/VX_cache.v
@@ -1,5 +1,7 @@
 `include "VX_cache_config.v"

+`include "VX_cache_config.v"
+

 module VX_cache (
 	input wire clk,