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simx timing simulation refactoring

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This commit is contained in:
Blaise Tine
2021-11-14 08:52:34 -05:00
parent 9656779d48
commit 808bddb586
22 changed files with 1123 additions and 903 deletions
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70
sim/simX/scoreboard.h
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@@ -10,6 +10,7 @@ private:
std::vector<RegMask> in_use_iregs_;
std::vector<RegMask> in_use_fregs_;
std::vector<RegMask> in_use_vregs_;
std::unordered_map<uint32_t, uint64_t> owners_;
public:
Scoreboard(const ArchDef &arch)
@@ -29,42 +30,87 @@ public:
|| (state.used_fregs & in_use_fregs_.at(state.wid)) != 0
|| (state.used_vregs & in_use_vregs_.at(state.wid)) != 0;
}
std::vector<uint64_t> owners(const pipeline_state_t& state) const {
std::vector<uint64_t> out;
{
uint32_t r = 0;
auto used_iregs = state.used_iregs & in_use_iregs_.at(state.wid);
while (used_iregs.any()) {
if (used_iregs.test(0)) {
uint32_t tag = (r << 16) | (state.wid << 4) | (int)RegType::Integer;
out.push_back(owners_.at(tag));
}
used_iregs >>= 1;
++r;
}
}
{
uint32_t r = 0;
auto used_fregs = state.used_fregs & in_use_fregs_.at(state.wid);
while (used_fregs.any()) {
if (used_fregs.test(0)) {
uint32_t tag = (r << 16) | (state.wid << 4) | (int)RegType::Float;
out.push_back(owners_.at(tag));
}
used_fregs >>= 1;
++r;
}
}
{
uint32_t r = 0;
auto used_vregs = state.used_vregs & in_use_vregs_.at(state.wid);
while (used_vregs.any()) {
if (used_vregs.test(0)) {
uint32_t tag = (r << 16) | (state.wid << 4) | (int)RegType::Vector;
out.push_back(owners_.at(tag));
}
used_vregs >>= 1;
++r;
}
}
return std::move(out);
}
void reserve(const pipeline_state_t& state) {
if (!state.rdest)
return;
if (!state.wb)
return;
switch (state.rdest_type) {
case 1:
case RegType::Integer:
in_use_iregs_.at(state.wid).set(state.rdest);
break;
case 2:
case RegType::Float:
in_use_fregs_.at(state.wid).set(state.rdest);
break;
case 3:
case RegType::Vector:
in_use_vregs_.at(state.wid).set(state.rdest);
break;
default:
break;
}
}
uint32_t tag = (state.rdest << 16) | (state.wid << 4) | (int)state.rdest_type;
assert(owners_.count(tag) == 0);
owners_[tag] = state.id;
}
void release(const pipeline_state_t& state) {
if (!state.rdest)
return;
if (!state.wb)
return;
switch (state.rdest_type) {
case 1:
case RegType::Integer:
in_use_iregs_.at(state.wid).reset(state.rdest);
break;
case 2:
case RegType::Float:
in_use_fregs_.at(state.wid).reset(state.rdest);
break;
case 3:
case RegType::Vector:
in_use_vregs_.at(state.wid).reset(state.rdest);
break;
default:
break;
}
uint32_t tag = (state.rdest << 16) | (state.wid << 4) | (int)state.rdest_type;
owners_.erase(tag);
}
};