From 7fc5b6a374c59d3bde02a46284d8a23c7aea7e27 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Wed, 1 May 2024 21:35:53 -0700
Subject: [PATCH] tensor: Fix elaboration error on VCS

---
 hw/rtl/core/VX_operands.sv      | 9 +++++----
 hw/rtl/core/VX_reduce_unit.sv   | 2 +-
 hw/rtl/core/VX_uop_sequencer.sv | 4 ++--
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/hw/rtl/core/VX_operands.sv b/hw/rtl/core/VX_operands.sv
index c59982b2..bccd47d9 100644
--- a/hw/rtl/core/VX_operands.sv
+++ b/hw/rtl/core/VX_operands.sv
@@ -308,10 +308,11 @@ module VX_operands import VX_gpu_pkg::*; #(
 
                 if (cycle == 32'd25000) begin
                     for (integer k = 0; k < `NUM_REGS * ISSUE_RATIO; ++k) begin
-                        integer warp = i * ISSUE_RATIO + (k / `NUM_REGS);
-                        integer thread = j;
-                        integer register = k % `NUM_REGS;
-                        $display("warp %0d, thread %0d, register %0d: %0x", warp, thread, register, gpr_ram.ram[k]);
+                        $display("warp %0d, thread %0d, register %0d: %0x",
+                          i * ISSUE_RATIO + (k / `NUM_REGS),
+                          j,
+                          k % `NUM_REGS,
+                          gpr_ram.ram[k]);
                     end
                 end
             end
diff --git a/hw/rtl/core/VX_reduce_unit.sv b/hw/rtl/core/VX_reduce_unit.sv
index 37610bcf..29ae2e4c 100644
--- a/hw/rtl/core/VX_reduce_unit.sv
+++ b/hw/rtl/core/VX_reduce_unit.sv
@@ -252,7 +252,7 @@ module VX_reduce_unit #(
 
     VX_elastic_buffer #(
         .DATAW(NUM_LANES + PID_WIDTH + 1 + 1),
-        .SIZE(NUM_PACKETS),
+        .SIZE(NUM_PACKETS)
     ) tmask_pid_store (
         .clk(clk),
         .reset(reset),
diff --git a/hw/rtl/core/VX_uop_sequencer.sv b/hw/rtl/core/VX_uop_sequencer.sv
index 3d2bb233..f0493a91 100644
--- a/hw/rtl/core/VX_uop_sequencer.sv
+++ b/hw/rtl/core/VX_uop_sequencer.sv
@@ -63,6 +63,8 @@ module VX_uop_sequencer import VX_gpu_pkg::*; (
     localparam HMMA_SET3_STEP3_1 = UPC_BITS'(38);
     // register layout: f0-f7 used for A, f8-f15 used for B, f16-f23 used for C
 
+    logic [UPC_BITS-1:0] upc, upc_r, upc_n;
+
     always @(*) begin
         case (upc)
             `include "VX_tensor_ucode.vh"
@@ -72,8 +74,6 @@ module VX_uop_sequencer import VX_gpu_pkg::*; (
         endcase
     end
 
-    logic [UPC_BITS-1:0] upc, upc_r, upc_n;
-
     wire [UBR_BITS-1:0] ubr = uop[UOP_TABLE_WIDTH-1:UOP_TABLE_WIDTH-UBR_BITS];
     wire [UPC_BITS-1:0] next_upc = uop[UOP_TABLE_WIDTH-UBR_BITS-1:UOP_TABLE_WIDTH-UBR_BITS-UPC_BITS];