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Fixed AA d_cache sizing errors

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This commit is contained in:
felsabbagh3
2019-11-11 15:20:58 -05:00
parent 0ad491f20e
commit 7ed88ce4c1
4 changed files with 210 additions and 50 deletions
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9
rtl/cache/VX_cache_data.v vendored
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@@ -100,6 +100,7 @@ module VX_cache_data
`else
wire[IND_SIZE_END:IND_SIZE_START] use_addr = addr;
wire cena = 1;
@@ -127,11 +128,11 @@ module VX_cache_data
.SOB(),
.CLKA(clk),
.CENA(cena),
.AA(addr),
.AA(use_addr),
.CLKB(clk),
.CENB(cenb_d),
.WENB(write_bit_mask_d),
.AB(addr),
.AB(use_addr),
.DB(wdata_d),
.EMAA(3'b011),
.EMASA(1'b0),
@@ -199,11 +200,11 @@ module VX_cache_data
.SOB(),
.CLKA(clk),
.CENA(cena),
.AA(addr),
.AA(use_addr),
.CLKB(clk),
.CENB(cenb_m),
// .WENB(write_bit_mask_m),
.AB(addr),
.AB(use_addr),
.DB(wdata_m),
.EMAA(3'b011),
.EMASA(1'b0),