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Modifications to allow 64-bit riscv tests to run on travis CI

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This commit is contained in:
Santosh Srivatsan
2022-01-27 15:55:19 -05:00
parent 7aa93a735d
commit 7e3a2fdb0f
10 changed files with 125 additions and 299 deletions
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9
sim/simx/decode.cpp
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@@ -488,9 +488,9 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
case Opcode::I_INST:
if (func3 == 0x1 || func3 == 0x5) {
// int5 (XLEN = 32) / int6 (XLEN = 64)
int shamt_width = log2up(XLEN);
int shamt = ((func7 & 0x1) << 5) | rs2;
instr->setImm(sext(shamt, shamt_width));
XWord shamt_mask = (1 << log2up(XLEN)) - 1;
XWord shamt = (((func7 & 0x1) << 5) | rs2) & shamt_mask;
instr->setImm(shamt);
} else {
// int12
instr->setImm(sext(code >> shift_rs2_, 12));
@@ -499,7 +499,8 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
case Opcode::I_INST_64:
if (func3 == 0x1 || func3 == 0x5) {
// int5
instr->setImm(sext64(rs2, 5));
XWord shamt = rs2;
instr->setImm(shamt);
} else {
// int12
instr->setImm(sext64(code >> shift_rs2_, 12));

24
sim/simx/execute.cpp
View File

@@ -256,15 +256,18 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
// RV32I: XOR
rddata[t] = rsdata[t][0] ^ rsdata[t][1];
break;
case 5:
case 5: {
XWord shamt_mask = (1 << log2up(XLEN)) - 1;
XWord shamt = rsdata[t][1] & shamt_mask;
if (func7) {
// RV32I: SRA
rddata[t] = XWordI(rsdata[t][0]) >> XWordI(rsdata[t][1]);
rddata[t] = XWordI(rsdata[t][0]) >> shamt;
} else {
// RV32I: SRL
rddata[t] = XWord(rsdata[t][0]) >> XWord(rsdata[t][1]);
rddata[t] = XWord(rsdata[t][0]) >> shamt;
}
break;
}
case 6:
// RV32I: OR
rddata[t] = rsdata[t][0] | rsdata[t][1];
@@ -315,7 +318,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
rddata[t] = result;
} else {
// RV64I: SRLI
XWord result = rsdata[t][0] >> immsrc;
XWord result = XWord(rsdata[t][0]) >> immsrc;
rddata[t] = result;
}
break;
@@ -413,15 +416,18 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
// RV64I: SLLW
rddata[t] = sext64((Word)rsdata[t][0] << (Word)rsdata[t][1], 32);
break;
case 5:
case 5: {
Word shamt_mask = 0x1F;
Word shamt = rsdata[t][1] & shamt_mask;
if (func7) {
// RV64I: SRAW
rddata[t] = sext64((WordI)rsdata[t][0] >> (WordI)rsdata[t][1], 32);
rddata[t] = sext64((WordI)rsdata[t][0] >> shamt, 32);
} else {
// RV64I: SRLW
rddata[t] = sext64((Word)rsdata[t][0] >> (Word)rsdata[t][1], 32);
rddata[t] = sext64((Word)rsdata[t][0] >> shamt, 32);
}
break;
}
default:
std::abort();
}
@@ -449,11 +455,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
case 5:
if (func7) {
// RV64I: SRAIW
XWord result = sext64((WordI)rsdata[t][0] >> (WordI)immsrc, 32);
XWord result = sext64((WordI)rsdata[t][0] >> immsrc, 32);
rddata[t] = result;
} else {
// RV64I: SRLIW
XWord result = sext64((Word)rsdata[t][0] >> (Word)immsrc, 32);
XWord result = sext64((Word)rsdata[t][0] >> immsrc, 32);
rddata[t] = result;
}
break;