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Change result type for dpi calls from wire -> reg

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VCS requires the output of the dpi calls to be of a type that can come
at the LHS of a procedural assignment, i.e. reg type.  Seems to be a
different requirement from Verilator.
This commit is contained in:
Hansung Kim
2023-11-15 19:26:12 -08:00
parent d2d7ee61bb
commit 7e0b63a3b3
2 changed files with 25 additions and 25 deletions
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4
hw/rtl/core/VX_muldiv_unit.sv
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@@ -69,7 +69,7 @@ module VX_muldiv_unit #(
wire mul_fire_in = mul_valid_in && mul_ready_in;
for (genvar i = 0; i < NUM_LANES; ++i) begin
wire [`XLEN-1:0] mul_resultl, mul_resulth;
reg [`XLEN-1:0] mul_resultl, mul_resulth;
wire [`XLEN-1:0] mul_in1 = is_alu_w ? (execute_if.data.rs1_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs1_data[i];
wire [`XLEN-1:0] mul_in2 = is_alu_w ? (execute_if.data.rs2_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs2_data[i];
always @(*) begin
@@ -230,7 +230,7 @@ module VX_muldiv_unit #(
wire div_fire_in = div_valid_in && div_ready_in;
for (genvar i = 0; i < NUM_LANES; ++i) begin
wire [`XLEN-1:0] div_quotient, div_remainder;
reg [`XLEN-1:0] div_quotient, div_remainder;
always @(*) begin
dpi_idiv (div_fire_in, is_signed_op, div_in1[i], div_in2[i], div_quotient, div_remainder);
end