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pre-submission changes

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This commit is contained in:
Richard Yan
2024-07-20 23:33:56 -07:00
parent 1833e8a176
commit 7d422cc9b0
4 changed files with 170 additions and 29 deletions
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1
hw/rtl/VX_platform.vh
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@@ -38,7 +38,6 @@
`ifdef SYNTHESIS `ifdef SYNTHESIS
`define FPU_FPNEW `define FPU_FPNEW
`define FIRESIM
`endif // SYNTHESIS `endif // SYNTHESIS
`ifdef SV_DPI `ifdef SV_DPI

37
hw/rtl/cache/VX_cache_bank.sv vendored
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@@ -434,10 +434,13 @@ module VX_cache_bank #(
wire [REQ_SEL_WIDTH-1:0] crsq_idx; wire [REQ_SEL_WIDTH-1:0] crsq_idx;
wire [TAG_WIDTH-1:0] crsq_tag; wire [TAG_WIDTH-1:0] crsq_tag;
logic [REQ_SEL_WIDTH-1:0] req_idx_st2;
logic [TAG_WIDTH-1:0] tag_st2;
assign crsq_valid = do_read_hit_st1 || do_replay_rd_st1; assign crsq_valid = do_read_hit_st1 || do_replay_rd_st1;
assign crsq_idx = req_idx_st1; assign crsq_idx = req_idx_st1; // req_idx_st2;
assign crsq_data = read_data_st1; assign crsq_data = read_data_st1;
assign crsq_tag = tag_st1; assign crsq_tag = tag_st1; // tag_st2;
`RESET_RELAY (crsp_reset, reset); `RESET_RELAY (crsp_reset, reset);
@@ -451,10 +454,40 @@ module VX_cache_bank #(
.valid_in (crsq_valid && ~rdw_hazard_st1), .valid_in (crsq_valid && ~rdw_hazard_st1),
.ready_in (crsq_ready), .ready_in (crsq_ready),
.data_in ({crsq_tag, crsq_data, crsq_idx}), .data_in ({crsq_tag, crsq_data, crsq_idx}),
// .data_out (),
.data_out ({core_rsp_tag, core_rsp_data, core_rsp_idx}), .data_out ({core_rsp_tag, core_rsp_data, core_rsp_idx}),
.valid_out (core_rsp_valid), .valid_out (core_rsp_valid),
.ready_out (core_rsp_ready) .ready_out (core_rsp_ready)
); );
/*
logic sh_fire_in, sh_val_out;
logic [TAG_WIDTH + `CS_WORD_WIDTH + REQ_SEL_WIDTH - 1 : 0] fake_dout;
always @(posedge clk) begin
if (crsp_reset) begin
sh_fire_in <= 1'b0;
req_idx_st2 <= '0;
tag_st2 <= '0;
end else begin
sh_fire_in <= crsq_valid && (~rdw_hazard_st1) && crsq_ready;
req_idx_st2 <= req_idx_st1;
tag_st2 <= tag_st1;
assert(sh_val_out == core_rsp_valid);
end
end
// $assert(CRSQ_SIZE == 2);
VX_stream_buffer_comb #(
.DATAW (TAG_WIDTH + `CS_WORD_WIDTH + REQ_SEL_WIDTH),
) core_resp_queue_shadow (
.clk (clk),
.reset (crsp_reset),
.valid_in (sh_fire_in),
.ready_in (),
.data_in ({crsq_tag, crsq_data, crsq_idx}),
.data_out ({core_rsp_tag, core_rsp_data, core_rsp_idx}),
.valid_out (sh_val_out),
.ready_out (core_rsp_ready)
);*/
assign crsq_stall = crsq_valid && ~crsq_ready; assign crsq_stall = crsq_valid && ~crsq_ready;

80
hw/rtl/libs/VX_dp_ram.sv
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@@ -162,10 +162,10 @@ module VX_dp_ram #(
end else begin end else begin
`ifndef FIRESIM `ifndef FIRESIM
if (DATAW == 1024 && SIZE == 16) begin // dcache data if (DATAW == 1024 && SIZE == 16) begin // dcache data
dcache_data ram ( (* dont_touch = "yes" *) dcache_data ram (
.R0_addr(raddr), .R0_addr(raddr),
.R0_clk(clk), .R0_clk(clk),
.R0_data(rdata), .R0_data(/*rdata*/),
.R0_en(read), .R0_en(read),
.W0_addr(waddr), .W0_addr(waddr),
.W0_clk(clk), .W0_clk(clk),
@@ -174,10 +174,10 @@ module VX_dp_ram #(
.W0_mask(wren) .W0_mask(wren)
); );
end else if (DATAW == 305 && SIZE == 8) begin // mshr end else if (DATAW == 305 && SIZE == 8) begin // mshr
cache_mshr ram ( (* dont_touch = "yes" *) cache_mshr ram (
.R0_addr(raddr), .R0_addr(raddr),
.R0_clk(clk), .R0_clk(clk),
.R0_data(rdata), .R0_data(/*rdata*/),
.R0_en(read), .R0_en(read),
.W0_addr(waddr), .W0_addr(waddr),
.W0_clk(clk), .W0_clk(clk),
@@ -185,10 +185,10 @@ module VX_dp_ram #(
.W0_en(write) .W0_en(write)
); );
end else if (DATAW == 24 && SIZE == 16) begin // dcache tags end else if (DATAW == 24 && SIZE == 16) begin // dcache tags
dcache_tags ram ( (* dont_touch = "yes" *) dcache_tags ram (
.R0_addr(raddr), .R0_addr(raddr),
.R0_clk(clk), .R0_clk(clk),
.R0_data(rdata), .R0_data(/*rdata*/),
.R0_en(read), .R0_en(read),
.W0_addr(waddr), .W0_addr(waddr),
.W0_clk(clk), .W0_clk(clk),
@@ -196,10 +196,10 @@ module VX_dp_ram #(
.W0_en(write) .W0_en(write)
); );
end else if (DATAW == 1024 && SIZE == 128) begin // icache data end else if (DATAW == 1024 && SIZE == 128) begin // icache data
icache_data ram ( (* dont_touch = "yes" *) icache_data ram (
.R0_addr(raddr), .R0_addr(raddr),
.R0_clk(clk), .R0_clk(clk),
.R0_data(rdata), .R0_data(/*rdata*/),
.R0_en(read), .R0_en(read),
.W0_addr(waddr), .W0_addr(waddr),
.W0_clk(clk), .W0_clk(clk),
@@ -208,17 +208,28 @@ module VX_dp_ram #(
.W0_mask(wren) .W0_mask(wren)
); );
end else if (DATAW == 21 && SIZE == 128) begin // icache tags end else if (DATAW == 21 && SIZE == 128) begin // icache tags
icache_tags ram ( (* dont_touch = "yes" *) icache_tags ram (
.R0_addr(raddr), .R0_addr(raddr),
.R0_clk(clk), .R0_clk(clk),
.R0_data(rdata), .R0_data(/*rdata*/),
.R0_en(read), .R0_en(read),
.W0_addr(waddr), .W0_addr(waddr),
.W0_clk(clk), .W0_clk(clk),
.W0_data(wdata), .W0_data(wdata),
.W0_en(write) .W0_en(write)
); );
end else begin end else if (DATAW == 32 && SIZE == 64) begin // register file
(* dont_touch = "yes" *) rf_bank ram (
.R0_addr(raddr),
.R0_clk(clk),
.R0_data(/*rdata*/),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write)
);
end // else begin
`endif `endif
if (OUT_REG != 0) begin if (OUT_REG != 0) begin
reg [DATAW-1:0] ram [SIZE-1:0]; reg [DATAW-1:0] ram [SIZE-1:0];
@@ -264,7 +275,7 @@ module VX_dp_ram #(
end end
end end
`ifndef FIRESIM `ifndef FIRESIM
end // end
`endif `endif
end end
`endif `endif
@@ -293,6 +304,51 @@ module VX_dp_ram #(
assign rdata = ram[raddr]; assign rdata = ram[raddr];
end end
end else begin end else begin
if (DATAW == 305 && SIZE == 8) begin // mshr
(* dont_touch = "yes" *) cache_mshr ram (
.R0_addr(raddr),
.R0_clk(clk),
.R0_data(/*rdata*/),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write)
);
end else if (DATAW == 24 && SIZE == 16) begin // dcache tags
(* dont_touch = "yes" *) dcache_tags ram (
.R0_addr(raddr),
.R0_clk(clk),
.R0_data(/*rdata*/),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write)
);
end else if (DATAW == 21 && SIZE == 128) begin // icache tags
(* dont_touch = "yes" *) icache_tags ram (
.R0_addr(raddr),
.R0_clk(clk),
.R0_data(/*rdata*/),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write)
);
end else if (DATAW == 32 && SIZE == 64) begin // register file
(* dont_touch = "yes" *) rf_bank ram (
.R0_addr(raddr),
.R0_clk(clk),
.R0_data(/*rdata*/),
.R0_en(read),
.W0_addr(waddr),
.W0_clk(clk),
.W0_data(wdata),
.W0_en(write)
);
end // else begin
if (OUT_REG != 0) begin if (OUT_REG != 0) begin
reg [DATAW-1:0] ram [SIZE-1:0]; reg [DATAW-1:0] ram [SIZE-1:0];
reg [DATAW-1:0] rdata_r; reg [DATAW-1:0] rdata_r;

53
hw/rtl/libs/VX_stream_buffer.sv
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@@ -123,6 +123,59 @@ module VX_stream_buffer #(
end end
end end
endmodule
module VX_stream_buffer_comb #(
parameter DATAW = 1,
parameter OUT_REG = 0,
parameter PASSTHRU = 0
) (
input wire clk,
input wire reset,
input wire valid_in,
output wire ready_in,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out,
input wire ready_out,
output wire valid_out
);
reg [1:0][DATAW-1:0] shift_reg;
reg valid_out_r, ready_in_r, rd_ptr_r;
reg bypass;
wire push = valid_in && ready_in;
wire pop = (valid_out_r || valid_in) && ready_out;
always @(posedge clk) begin
if (reset) begin
valid_out_r <= 0;
ready_in_r <= 1;
rd_ptr_r <= 1;
end else begin
if (push) begin
if (!pop) begin
ready_in_r <= rd_ptr_r;
valid_out_r <= 1;
end
end else if (pop) begin
ready_in_r <= 1;
valid_out_r <= rd_ptr_r;
end
rd_ptr_r <= rd_ptr_r ^ (push ^ pop);
end
end
always @(posedge clk) begin
if (push) begin
shift_reg[1] <= shift_reg[0];
shift_reg[0] <= data_in;
end
end
assign ready_in = ready_in_r;
assign valid_out = valid_out_r || valid_in;
assign data_out = valid_out_r ? shift_reg[rd_ptr_r] : data_in;
endmodule endmodule
`TRACING_ON `TRACING_ON