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reset network refactoring

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This commit is contained in:
Blaise Tine
2021-07-15 11:34:55 -07:00
parent 22cf698e69
commit 7d01be367c
11 changed files with 68 additions and 137 deletions
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16
hw/rtl/fp_cores/VX_fp_div.v
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@@ -33,18 +33,6 @@ module VX_fp_div #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
`ifndef VERILATOR
wire [LANES-1:0] fdiv_reset;
VX_reset_relay #(
.DEPTH (LANES > 1),
.NUM_NODES (LANES)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fdiv_reset)
);
`endif
for (genvar i = 0; i < LANES; i++) begin
`ifdef VERILATOR
reg [31:0] r;
@@ -67,9 +55,11 @@ module VX_fp_div #(
.data_out (result[i])
);
`else
`RESET_RELAY (fdiv_reset);
acl_fdiv fdiv (
.clk (clk),
.areset (fdiv_reset[i]),
.areset (fdiv_reset),
.en (enable),
.a (dataa[i]),
.b (datab[i]),

16
hw/rtl/fp_cores/VX_fp_fma.v
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@@ -39,18 +39,6 @@ module VX_fp_fma #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
`ifndef VERILATOR
wire [LANES-1:0] fma_reset;
VX_reset_relay #(
.DEPTH (LANES > 1),
.NUM_NODES (LANES)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fma_reset)
);
`endif
for (genvar i = 0; i < LANES; i++) begin
reg [31:0] a, b, c;
@@ -96,9 +84,11 @@ module VX_fp_fma #(
.data_out (result[i])
);
`else
`RESET_RELAY (fma_reset);
acl_fmadd fmadd (
.clk (clk),
.areset (fma_reset[i]),
.areset (fma_reset),
.en (enable),
.a (a),
.b (b),

16
hw/rtl/fp_cores/VX_fp_sqrt.v
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@@ -32,18 +32,6 @@ module VX_fp_sqrt #(
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
`ifndef VERILATOR
wire [LANES-1:0] fsqrt_reset;
VX_reset_relay #(
.DEPTH (LANES > 1),
.NUM_NODES (LANES)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fsqrt_reset)
);
`endif
for (genvar i = 0; i < LANES; i++) begin
`ifdef VERILATOR
reg [31:0] r;
@@ -66,9 +54,11 @@ module VX_fp_sqrt #(
.data_out (result[i])
);
`else
`RESET_RELAY (fsqrt_reset);
acl_fsqrt fsqrt (
.clk (clk),
.areset (fsqrt_reset[i]),
.areset (fsqrt_reset),
.en (enable),
.a (dataa[i]),
.q (result[i])

23
hw/rtl/fp_cores/VX_fpu_fpga.v
View File

@@ -71,21 +71,18 @@ module VX_fpu_fpga #(
endcase
end
wire [NUM_FPC-1:0] fpu_reset;
VX_reset_relay #(
.NUM_NODES(NUM_FPC)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o (fpu_reset)
);
`RESET_RELAY (fma_reset);
`RESET_RELAY (div_reset);
`RESET_RELAY (sqrt_reset);
`RESET_RELAY (cvt_reset);
`RESET_RELAY (ncp_reset);
VX_fp_fma #(
.TAGW (TAGW),
.LANES(`NUM_THREADS)
) fp_fma (
.clk (clk),
.reset (fpu_reset[FPU_FMA]),
.reset (fma_reset),
.valid_in (valid_in && (core_select == FPU_FMA)),
.ready_in (per_core_ready_in[FPU_FMA]),
.tag_in (tag_in),
@@ -109,7 +106,7 @@ module VX_fpu_fpga #(
.LANES(`NUM_THREADS)
) fp_div (
.clk (clk),
.reset (fpu_reset[FPU_DIV]),
.reset (div_reset),
.valid_in (valid_in && (core_select == FPU_DIV)),
.ready_in (per_core_ready_in[FPU_DIV]),
.tag_in (tag_in),
@@ -129,7 +126,7 @@ module VX_fpu_fpga #(
.LANES(`NUM_THREADS)
) fp_sqrt (
.clk (clk),
.reset (fpu_reset[FPU_SQRT]),
.reset (sqrt_reset),
.valid_in (valid_in && (core_select == FPU_SQRT)),
.ready_in (per_core_ready_in[FPU_SQRT]),
.tag_in (tag_in),
@@ -148,7 +145,7 @@ module VX_fpu_fpga #(
.LANES(`NUM_THREADS)
) fp_cvt (
.clk (clk),
.reset (fpu_reset[FPU_CVT]),
.reset (cvt_reset),
.valid_in (valid_in && (core_select == FPU_CVT)),
.ready_in (per_core_ready_in[FPU_CVT]),
.tag_in (tag_in),
@@ -169,7 +166,7 @@ module VX_fpu_fpga #(
.LANES(`NUM_THREADS)
) fp_ncomp (
.clk (clk),
.reset (fpu_reset[FPU_NCP]),
.reset (ncp_reset),
.valid_in (valid_in && (core_select == FPU_NCP)),
.ready_in (per_core_ready_in[FPU_NCP]),
.tag_in (tag_in),