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reset network refactoring

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This commit is contained in:
Blaise Tine
2021-07-15 11:34:55 -07:00
parent 22cf698e69
commit 7d01be367c
11 changed files with 68 additions and 137 deletions
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16
hw/rtl/VX_mem_unit.v
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@@ -61,16 +61,10 @@ module VX_mem_unit # (
.NUM_REQS (`DNUM_REQS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH-`SM_ENABLE)
) dcache_rsp_if();
) dcache_rsp_if();
wire icache_reset, dcache_reset, smem_reset;
VX_reset_relay #(
.NUM_NODES (3)
) reset_relay (
.clk (clk),
.reset (reset),
.reset_o ({icache_reset, dcache_reset, smem_reset})
);
`RESET_RELAY (icache_reset);
`RESET_RELAY (dcache_reset);
VX_cache #(
.CACHE_ID (`ICACHE_ID),
@@ -214,6 +208,8 @@ module VX_mem_unit # (
.core_rsp_if (dcache_core_rsp_if)
);
`RESET_RELAY (smem_reset);
VX_shared_mem #(
.CACHE_ID (`SCACHE_ID),
.CACHE_SIZE (`SMEM_SIZE),
@@ -249,8 +245,6 @@ module VX_mem_unit # (
.core_rsp_ready (smem_rsp_if.ready)
);
end else begin
`UNUSED_VAR (smem_reset)
// core to D-cache request
assign dcache_req_if.valid = dcache_core_req_if.valid;
assign dcache_req_if.addr = dcache_core_req_if.addr;