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pipeline refactoring: centralized issue buffer

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This commit is contained in:
Blaise Tine
2020-07-26 11:21:08 -04:00
parent 1f63f9da25
commit 7c86b68977
62 changed files with 923 additions and 820 deletions
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3
hw/simulate/Makefile
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@@ -15,7 +15,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE
DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CORE_REQ_INFO
#DBG_FLAGS += -DDBG_CORE_REQ_INFO
INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/cache -I../rtl/fp_cores -I../rtl/simulate
@@ -35,7 +35,6 @@ VF += -cc Vortex.v -top-module Vortex
VF += verilator.vlt
DBG += -DVCD_OUTPUT $(DBG_FLAGS)
DBG += -DDBG_CORE_REQ_INFO
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')

5
hw/simulate/simulator.cpp
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@@ -11,7 +11,7 @@ double sc_time_stamp() {
Simulator::Simulator() {
// force random values for unitialized signals
Verilated::randReset(1);
Verilated::randReset(2);
// Turn off assertion before reset
Verilated::assertOn(false);
@@ -24,7 +24,8 @@ Simulator::Simulator() {
#ifdef VCD_OUTPUT
Verilated::traceEverOn(true);
trace_ = new VerilatedVcdC;
trace_ = new VerilatedVcdC();
trace_->set_time_unit("1ns");
vortex_->trace(trace_, 99);
trace_->open("trace.vcd");
#endif