pipeline refactoring: centralized issue buffer

hw/rtl/interfaces/VX_mul_req_if.v

@@ -3,21 +3,21 @@
 
 `include "VX_define.vh"
 
+`ifndef EXT_M_ENABLE
+    `IGNORE_WARNINGS_BEGIN
+`endif
+
 interface VX_mul_req_if ();
 
-    wire [`NUM_THREADS-1:0]     valid;
-    wire [`NW_BITS-1:0]         warp_num;
-    wire [31:0]                 curr_PC;
+    wire                    valid;
+    wire [`ISTAG_BITS-1:0]  issue_tag;
     
-    wire [`MUL_BITS-1:0]        mul_op;
-
-    wire                        wb;
-    wire [`NR_BITS-1:0]         rd;    
+    wire [`MUL_BITS-1:0]    mul_op;
 
     wire [`NUM_THREADS-1:0][31:0] rs1_data;
     wire [`NUM_THREADS-1:0][31:0] rs2_data;
         
-    wire                        ready;
+    wire                    ready;
 
 endinterface