pipeline refactoring: centralized issue buffer

hw/rtl/interfaces/VX_lsu_req_if.v

@@ -5,20 +5,22 @@
 
 interface VX_lsu_req_if ();
 
-    wire [`NUM_THREADS-1:0]         valid;
+    wire                            valid;
+    wire [`NUM_THREADS-1:0]         thread_mask;
+    wire [`ISTAG_BITS-1:0]          issue_tag;
     wire [`NW_BITS-1:0]             warp_num;
     wire [31:0]                     curr_PC;
 
     wire                            rw; 
     wire [`BYTEEN_BITS-1:0]         byteen;
-        
-    wire                            wb; 
-    wire [`NR_BITS-1:0]             rd; 
 
     wire [`NUM_THREADS-1:0][31:0]   store_data;
     wire [`NUM_THREADS-1:0][31:0]   base_addr;    
     wire [31:0]                     offset;   
-    
+
+    wire [`NR_BITS-1:0]             rd;
+    wire                            wb;
+        
     wire                            ready;
 
 endinterface