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pipeline refactoring: centralized issue buffer

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This commit is contained in:
Blaise Tine
2020-07-26 11:21:08 -04:00
parent 1f63f9da25
commit 7c86b68977
62 changed files with 923 additions and 820 deletions
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11
hw/rtl/interfaces/VX_alu_req_if.v
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@@ -5,18 +5,17 @@
interface VX_alu_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [`ALU_BITS-1:0] alu_op;
wire wb;
wire [`NR_BITS-1:0] rd;
wire [`ALU_BITS-1:0] alu_op;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [31:0] offset;
wire [31:0] next_PC;

9
hw/rtl/interfaces/VX_commit_if.v
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@@ -5,12 +5,9 @@
interface VX_commit_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [`NUM_THREADS-1:0][31:0] data;
wire [`NR_BITS-1:0] rd;
wire wb;
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NUM_THREADS-1:0][31:0] data;
wire ready;
endinterface

43
hw/rtl/interfaces/VX_commit_is_if.v Normal file
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@@ -0,0 +1,43 @@
`ifndef VX_COMMIT_IS_IF
`define VX_COMMIT_IS_IF
`include "VX_define.vh"
typedef struct packed {
logic [`NW_BITS-1:0] warp_num;
logic [`NUM_THREADS-1:0] thread_mask;
logic [31:0] curr_PC;
logic [`NR_BITS-1:0] rd;
logic rd_is_fp;
logic wb;
} is_data_t;
interface VX_commit_is_if ();
wire alu_valid;
wire lsu_valid;
wire csr_valid;
wire mul_valid;
wire fpu_valid;
wire gpu_valid;
wire [`ISTAG_BITS-1:0] alu_tag;
wire [`ISTAG_BITS-1:0] lsu_tag;
wire [`ISTAG_BITS-1:0] csr_tag;
wire [`ISTAG_BITS-1:0] mul_tag;
wire [`ISTAG_BITS-1:0] fpu_tag;
wire [`ISTAG_BITS-1:0] gpu_tag;
`IGNORE_WARNINGS_BEGIN
is_data_t alu_data;
is_data_t lsu_data;
is_data_t csr_data;
is_data_t mul_data;
is_data_t fpu_data;
is_data_t gpu_data;
`IGNORE_WARNINGS_END
endinterface
`endif

3
hw/rtl/interfaces/VX_csr_req_if.v
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@@ -5,7 +5,8 @@
interface VX_csr_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;

3
hw/rtl/interfaces/VX_decode_if.v
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@@ -5,8 +5,9 @@
interface VX_decode_if ();
wire [`NUM_THREADS-1:0] valid;
wire valid;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0] thread_mask;
wire [31:0] curr_PC;
wire [31:0] next_PC;

4
hw/rtl/interfaces/VX_fpu_from_csr_if.v
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@@ -3,6 +3,10 @@
`include "VX_define.vh"
`ifndef EXTF_F_ENABLE
`IGNORE_WARNINGS_BEGIN
`endif
interface VX_fpu_from_csr_if ();
wire [`NW_BITS-1:0] warp_num;

12
hw/rtl/interfaces/VX_fpu_req_if.v
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@@ -3,19 +3,19 @@
`include "VX_define.vh"
`ifndef EXTF_F_ENABLE
`IGNORE_WARNINGS_BEGIN
`endif
interface VX_fpu_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [`FPU_BITS-1:0] fpu_op;
wire [`FRM_BITS-1:0] frm;
wire wb;
wire [`NR_BITS-1:0] rd;
wire rd_is_fp;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NUM_THREADS-1:0][31:0] rs3_data;

4
hw/rtl/interfaces/VX_fpu_to_csr_if.v
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@@ -3,6 +3,10 @@
`include "VX_define.vh"
`ifndef EXTF_F_ENABLE
`IGNORE_WARNINGS_BEGIN
`endif
interface VX_fpu_to_csr_if ();
wire valid;

15
hw/rtl/interfaces/VX_gpu_req_if.v
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@@ -5,17 +5,18 @@
interface VX_gpu_req_if();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`NW_BITS-1:0] warp_num;
wire [`GPU_BITS-1:0] gpu_op;
wire [`GPU_BITS-1:0] gpu_op;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [31:0] rs2_data;
wire [31:0] next_PC;
wire [31:0] rs2_data;
wire [31:0] next_PC;
wire ready;
wire ready;
endinterface

9
hw/rtl/interfaces/VX_ifetch_req_if.v
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@@ -5,10 +5,11 @@
interface VX_ifetch_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire ready;
wire valid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire ready;
endinterface

11
hw/rtl/interfaces/VX_ifetch_rsp_if.v
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@@ -5,11 +5,12 @@
interface VX_ifetch_rsp_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [31:0] instr;
wire ready;
wire valid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [31:0] instr;
wire ready;
endinterface

12
hw/rtl/interfaces/VX_lsu_req_if.v
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@@ -5,20 +5,22 @@
interface VX_lsu_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire valid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire rw;
wire [`BYTEEN_BITS-1:0] byteen;
wire wb;
wire [`NR_BITS-1:0] rd;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_addr;
wire [31:0] offset;
wire [`NR_BITS-1:0] rd;
wire wb;
wire ready;
endinterface

16
hw/rtl/interfaces/VX_mul_req_if.v
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@@ -3,21 +3,21 @@
`include "VX_define.vh"
`ifndef EXT_M_ENABLE
`IGNORE_WARNINGS_BEGIN
`endif
interface VX_mul_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire valid;
wire [`ISTAG_BITS-1:0] issue_tag;
wire [`MUL_BITS-1:0] mul_op;
wire wb;
wire [`NR_BITS-1:0] rd;
wire [`MUL_BITS-1:0] mul_op;
wire [`NUM_THREADS-1:0][31:0] rs1_data;
wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire ready;
wire ready;
endinterface

7
hw/rtl/interfaces/VX_warp_ctl_if.v
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@@ -12,17 +12,14 @@ interface VX_warp_ctl_if ();
wire wspawn;
wire [31:0] wspawn_pc;
wire [`NUM_WARPS-1:0] wspawn_new_active;
wire whalt;
wire [`NUM_WARPS-1:0] wspawn_wmask;
wire is_barrier;
wire [`NB_BITS-1:0] barrier_id;
wire [`NW_BITS:0] num_warps;
wire [`NW_BITS:0] barrier_num_warps;
wire is_split;
wire do_split;
wire [`NUM_THREADS-1:0] split_new_mask;
wire [`NUM_THREADS-1:0] split_later_mask;
wire [31:0] split_save_pc;

3
hw/rtl/interfaces/VX_wb_if.v
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@@ -5,7 +5,8 @@
interface VX_wb_if ();
wire [`NUM_THREADS-1:0] valid;
wire valid;
wire [`NUM_THREADS-1:0] thread_mask;
wire [`NW_BITS-1:0] warp_num;
wire [`NR_BITS-1:0] rd;
wire rd_is_fp;