pipeline refactoring: centralized issue buffer
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2
hw/rtl/cache/VX_cache.v
vendored
2
hw/rtl/cache/VX_cache.v
vendored
@@ -133,7 +133,7 @@ module VX_cache #(
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wire debug_core_req_wb;
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wire[`NR_BITS-1:0] debug_core_req_rd;
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wire[`NW_BITS-1:0] debug_core_req_warp_num;
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wire[`LOG2UP(CREQ_SIZE)-1:0] debug_core_req_idx;
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wire[`UP(CORE_TAG_ID_BITS)-1:0] debug_core_req_idx;
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/* verilator lint_on UNUSED */
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if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
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