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tex_unit update

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This commit is contained in:
Blaise Tine
2021-03-31 05:43:44 -04:00
parent 79fcdf7a28
commit 7b2f96bc6d
12 changed files with 687 additions and 651 deletions
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14
hw/rtl/VX_lsu_unit.v
View File

@@ -78,7 +78,7 @@ module VX_lsu_unit #(
wire [`NUM_THREADS-1:0] rsp_rem_mask_n;
reg [`NUM_THREADS-1:0] req_sent_mask;
wire req_sent_all;
wire sent_all_ready;
wire [`LSUQ_ADDR_BITS-1:0] mbuf_waddr, mbuf_raddr;
wire mbuf_full;
@@ -116,13 +116,13 @@ module VX_lsu_unit #(
.full (mbuf_full)
);
assign req_sent_all = (&(dcache_req_if.ready | req_sent_mask | ~req_tmask))
|| (req_is_dup & dcache_req_if.ready[0]);
assign sent_all_ready = (&(dcache_req_if.ready | req_sent_mask | ~req_tmask))
|| (req_is_dup & dcache_req_if.ready[0]);
always @(posedge clk) begin
if (reset || req_sent_all) begin
if (reset || sent_all_ready) begin
req_sent_mask <= 0;
end else if (!req_sent_all) begin
end else begin
req_sent_mask <= req_sent_mask | dcache_req_fire;
end
end
@@ -193,11 +193,11 @@ module VX_lsu_unit #(
assign dcache_req_if.tag = {`NUM_THREADS{req_tag}};
`endif
assign ready_in = req_ready_dep && req_sent_all;
assign ready_in = req_ready_dep && sent_all_ready;
// send store commit
wire is_store_rsp = req_valid && ~req_wb && req_sent_all;
wire is_store_rsp = req_valid && ~req_wb && sent_all_ready;
assign st_commit_if.valid = is_store_rsp;
assign st_commit_if.wid = req_wid;

6
hw/rtl/fp_cores/VX_fpu_dpi.v
View File

@@ -330,9 +330,9 @@ module VX_fpu_dpi #(
dpi_feq (dataa[i], datab[i], result_feq[i], fflags_feq[i]);
dpi_fmin (dataa[i], datab[i], result_fmin[i], fflags_fmin[i]);
dpi_fmax (dataa[i], datab[i], result_fmax[i], fflags_fmax[i]);
dpi_fsgnj (dataa[i], result_fsgnj[i]);
dpi_fsgnjn (dataa[i], result_fsgnjn[i]);
dpi_fsgnjx (dataa[i], result_fsgnjx[i]);
dpi_fsgnj (dataa[i], datab[i], result_fsgnj[i]);
dpi_fsgnjn (dataa[i], datab[i], result_fsgnjn[i]);
dpi_fsgnjx (dataa[i], datab[i], result_fsgnjx[i]);
result_fmv[i] = dataa[i];
end
end

12
hw/rtl/tex_unit/VX_tex_memory.v
View File

@@ -99,7 +99,7 @@ module VX_tex_memory #(
///////////////////////////////////////////////////////////////////////////
wire req_texel_valid;
wire req_texel_sent, last_texel_sent;
wire sent_all_ready, last_texel_sent;
wire req_texel_dup;
wire [`NUM_THREADS-1:0][29:0] req_texel_addr;
reg [1:0] req_texel_idx;
@@ -108,7 +108,7 @@ module VX_tex_memory #(
always @(posedge clk) begin
if (reset || last_texel_sent) begin
req_texel_idx <= 0;
end else if (req_texel_sent) begin
end else if (req_texel_valid && sent_all_ready) begin
req_texel_idx <= req_texel_idx + 1;
end
end
@@ -126,7 +126,7 @@ module VX_tex_memory #(
assign req_texel_dup = q_dup_reqs[req_texel_idx];
wire is_last_texel = (req_texel_idx == (q_req_filter ? 3 : 0));
assign last_texel_sent = req_texel_sent && is_last_texel;
assign last_texel_sent = req_texel_valid && sent_all_ready && is_last_texel;
// DCache Request
@@ -136,11 +136,11 @@ module VX_tex_memory #(
assign dcache_req_fire = dcache_req_if.valid & dcache_req_if.ready;
assign req_texel_sent = (&(dcache_req_if.ready | texel_sent_mask | ~q_req_tmask))
|| (req_texel_dup & dcache_req_if.ready[0]);
assign sent_all_ready = (&(dcache_req_if.ready | texel_sent_mask | ~q_req_tmask))
|| (req_texel_dup & dcache_req_if.ready[0]);
always @(posedge clk) begin
if (reset || req_texel_sent) begin
if (reset || sent_all_ready) begin
texel_sent_mask <= 0;
end else begin
texel_sent_mask <= texel_sent_mask | dcache_req_fire;