Packing data wires + ALU module

rtl/obj_dir/VVortex__Syms.cpp

@@ -0,0 +1,19 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Symbol table implementation internals
+
+#include "VVortex__Syms.h"
+#include "VVortex.h"
+
+// FUNCTIONS
+VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
+	// Setup locals
+	: __Vm_namep(namep)
+	, __Vm_didInit(false)
+	// Setup submodule names
+{
+    // Pointer to top level
+    TOPp = topp;
+    // Setup each module's pointers to their submodules
+    // Setup each module's pointer back to symbol table (for public functions)
+    TOPp->__Vconfigure(this, true);
+}