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minor update

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This commit is contained in:
Blaise Tine
2021-06-29 07:06:05 -07:00
parent cd387d2b5b
commit 7a4c4adeb1
3 changed files with 35 additions and 34 deletions
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6
doc/cache_subsystem.md
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@@ -8,7 +8,7 @@ The Vortex Cache Sub-system has the following main properties:
### Cache Hierarchy ### Cache Hierarchy
![Image of Cache Hierarchy](./Images/cache_hierarchy.png) ![Image of Cache Hierarchy](./images/cache_hierarchy.png)
- Cache can be configured to be any level in the hierarchy - Cache can be configured to be any level in the hierarchy
- Caches communicate via snooping - Caches communicate via snooping
@@ -18,7 +18,7 @@ The Vortex Cache Sub-system has the following main properties:
VX.cache.v is the top module of the cache verilog code located in the `/hw/rtl/cache` directory. VX.cache.v is the top module of the cache verilog code located in the `/hw/rtl/cache` directory.
![Image of Vortex Cache](./Images/vortex_cache_top_module.png) ![Image of Vortex Cache](./images/vortex_cache_top_module.png)
- Configurable (Cache size, number of banks, bank line size, etc.) - Configurable (Cache size, number of banks, bank line size, etc.)
- I/O signals - I/O signals
@@ -44,7 +44,7 @@ VX.cache.v is the top module of the cache verilog code located in the `/hw/rtl/c
VX_bank.v is the verilog code that handles cache bank functionality and is located in the `/hw/rtl/cache` directory. VX_bank.v is the verilog code that handles cache bank functionality and is located in the `/hw/rtl/cache` directory.
![Image of Vortex Cache Bank](./Images/vortex_bank.png) ![Image of Vortex Cache Bank](./images/vortex_bank.png)
- Allows for high throughput​ - Allows for high throughput​
- Each bank contains queues to hold requests to the cache​ - Each bank contains queues to hold requests to the cache​

61
doc/codebase.md
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@@ -2,33 +2,34 @@
The directory/file layout of the Vortex codebase is as followed: The directory/file layout of the Vortex codebase is as followed:
- `hw`: - `hw`:
- `unit_tests`: contains unit test for RTL of cache and queue - `rtl`: hardware rtl sources
- `syn`: contains all synthesis scripts (quartus and yosys) - `cache`: cache subsystem code
- `quartus`: contains synthesis scripts for Intel Quartus toolchain - `fp_cores`: floating point unit code
- `opae`: contains synthesis scripts for Intel OPAE FPGA - `interfaces`: interfaces for inter-module communication
- `simulate`: contains RTL simulator (verilator) - `libs`: general-purpose modules (i.e., encoder, arbiter, ...)
- `rtl`: contains rtl source code - `syn`: synthesis directory
- `cache`: contains cache subsystem code - `opae`: OPAE synthesis scripts
- `fp_cores`: contains floating point unit code - `quartus`: Quartus synthesis scripts
- `interfaces`: contains code that handles communication for each of the units of the microarchitecture - `synopsys`: Synopsys synthesis scripts
- `libs`: contains general-purpose modules (i.e., buffers, encoders, arbiters, pipe registers) - `yosys`: Yosys synthesis scripts
- `driver`: contains driver software implementation (software that is run on the host to communicate with the vortex processor) - `simulate`: baseline RTL simulator (used by RTLSIM)
- `include`: contains vortex.h which has the vortex API that is used by the drivers - `unit_tests`: unit tests for some hardware components
- `opae`: contains code for driver that runs on FPGA - `driver`: Host driver software
- `rtlsim`: contains code for driver that runs on local machine (driver built using verilator which converts rtl to c++ binary) - `include`: Vortex driver public headers
- `simx`: contains code for driver that runs on local machine (vortex) - `opae`: software driver that uses Intel OPAE
- `runtime`: contains software used inside kernel programs to expose GPGPU capabilities - `vlsim`: software driver that simulates Full RTL (include AFU)
- `include`: contains vortex API needed for runtime - `rtlsim`: software driver that simulates processor RTL
- `linker`: contains linker file for compiling kernels - `simx`: software driver that uses simX simulator
- `src`: contains implementation of vortex API (from include folder) - `runtime`: Kernel runtime software
- `simX`: contains simX, the cycle approximate simulator for vortex - `include`: Vortex runtime public headers
- `tests`: contains tests suite - `linker`: linker file for compiling kernels
- `runtime`: contains vortex runtime tests - `src`: runtime implementation
- `driver`: contains vortex driver tests - `simX`: cycle approximate simulator for vortex
- `opencl`: contains opencl tests and benchmarks - `tests`: tests repository.
- `riscv`: contains official riscv tests - `runtime`: runtime tests
- `regression`: contains regression tests - `regression`: regression tests
- `vector`: tests for vector instructions (not yet implemented) - `riscv`: RISC-V standard tests
- `ci`: contain tests to be run during continuous integration (Travis CI) - `opencl`: opencl benchmarks and tests
- `miscs`: contains miscellaneous stuffs - `ci`: continuous integration scripts
- `miscs`: miscellaneous resources.

2
doc/microarchitecture.md
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@@ -32,7 +32,7 @@ Vortex uses the SIMT (Single Instruction, Multiple Threads) execution model with
### Vortex Pipeline/Datapath ### Vortex Pipeline/Datapath
![Image of Vortex Microarchitecture](./Images/vortex_microarchitecture_v2.png) ![Image of Vortex Microarchitecture](./images/vortex_microarchitecture_v2.png)
Vortex has a 5-stage pipeline: FI | ID | Issue | EX | WB. Vortex has a 5-stage pipeline: FI | ID | Issue | EX | WB.