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tex_unit compiler fixes

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This commit is contained in:
Blaise Tine
2021-03-22 12:20:01 -04:00
parent 40e3e0105a
commit 79cbea0a13
5 changed files with 32 additions and 22 deletions
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3
hw/rtl/VX_define.vh
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@@ -293,7 +293,8 @@
`ifdef EXT_TEX_ENABLE `ifdef EXT_TEX_ENABLE
`define LSU_DACHE_TAG_BITS (`DBG_CACHE_REQ_MDATAW + `LSUQ_ADDR_BITS) `define LSU_DACHE_TAG_BITS (`DBG_CACHE_REQ_MDATAW + `LSUQ_ADDR_BITS)
`define TEX_DACHE_TAG_BITS (`DBG_CACHE_REQ_MDATAW + 2 + `LSUQ_ADDR_BITS) `define TEX_DACHE_TAG_BITS (`DBG_CACHE_REQ_MDATAW + 2 + `LSUQ_ADDR_BITS)
`define DCORE_TAG_WIDTH (`MAX(`LSU_DACHE_TAG_BITS, `TEX_DACHE_TAG_BITS) + 1) `define LSU_TEX_DACHE_TAG_BITS `MAX(`LSU_DACHE_TAG_BITS, `TEX_DACHE_TAG_BITS)
`define DCORE_TAG_WIDTH (`LSU_TEX_DACHE_TAG_BITS + 1)
`else `else
`define DCORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `DCORE_TAG_ID_BITS) `define DCORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `DCORE_TAG_ID_BITS)
`endif `endif

33
hw/rtl/VX_execute.v
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@@ -72,29 +72,38 @@ module VX_execute #(
.CORE_TAG_WIDTH(`TEX_DACHE_TAG_BITS) .CORE_TAG_WIDTH(`TEX_DACHE_TAG_BITS)
) tex_dcache_rsp_if(); ) tex_dcache_rsp_if();
VX_tex_csr_if tex_csr_if(); VX_tex_csr_if tex_csr_if();
wire [1:0] tmp; wire [`NUM_THREADS-1:0][`LSU_TEX_DACHE_TAG_BITS-1:0] lsu_tag_in;
`UNUSED_VAR (tmp) wire [`LSU_TEX_DACHE_TAG_BITS-1:0] lsu_tag_out;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
assign lsu_tag_in[i][`LSUQ_ADDR_BITS-1:0] = lsu_dcache_req_if.tag[i][`LSUQ_ADDR_BITS-1:0];
assign lsu_tag_in[i][`LSUQ_ADDR_BITS+:2] = '0;
assign lsu_tag_in[i][(`LSUQ_ADDR_BITS+2)+:`DBG_CACHE_REQ_MDATAW] = lsu_dcache_req_if.tag[i][`LSUQ_ADDR_BITS+:`DBG_CACHE_REQ_MDATAW];
end
assign lsu_dcache_rsp_if.tag[`LSUQ_ADDR_BITS-1:0] = lsu_tag_out[`LSUQ_ADDR_BITS-1:0];
assign lsu_dcache_rsp_if.tag[`LSUQ_ADDR_BITS+:`DBG_CACHE_REQ_MDATAW] = lsu_tag_out[(`LSUQ_ADDR_BITS+2)+:`DBG_CACHE_REQ_MDATAW];
`UNUSED_VAR (lsu_tag_out)
VX_tex_lsu_arb #( VX_tex_lsu_arb #(
.NUM_REQS (2), .NUM_REQS (2),
.LANES (`NUM_THREADS), .LANES (`NUM_THREADS),
.WORD_SIZE (4), .WORD_SIZE (4),
.TAG_IN_WIDTH (`MAX(`LSU_DACHE_TAG_BITS, `TEX_DACHE_TAG_BITS)), .TAG_IN_WIDTH (`LSU_TEX_DACHE_TAG_BITS),
.TAG_OUT_WIDTH (`DCORE_TAG_WIDTH) .TAG_OUT_WIDTH (`DCORE_TAG_WIDTH)
) tex_lsu_arb ( ) tex_lsu_arb (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
// Tex/LSU request // Tex/LSU request
.req_valid_in ({tex_dcache_req_if.valid, lsu_dcache_req_if.valid}), .req_valid_in ({tex_dcache_req_if.valid, lsu_dcache_req_if.valid}),
.req_rw_in ({tex_dcache_req_if.rw, lsu_dcache_req_if.rw}), .req_rw_in ({tex_dcache_req_if.rw, lsu_dcache_req_if.rw}),
.req_byteen_in ({tex_dcache_req_if.byteen, lsu_dcache_req_if.byteen}), .req_byteen_in ({tex_dcache_req_if.byteen, lsu_dcache_req_if.byteen}),
.req_addr_in ({tex_dcache_req_if.addr, lsu_dcache_req_if.addr}), .req_addr_in ({tex_dcache_req_if.addr, lsu_dcache_req_if.addr}),
.req_data_in ({tex_dcache_req_if.data, lsu_dcache_req_if.data}), .req_data_in ({tex_dcache_req_if.data, lsu_dcache_req_if.data}),
.req_tag_in ({tex_dcache_req_if.tag, {2'b0, lsu_dcache_req_if.tag}}), .req_tag_in ({tex_dcache_req_if.tag, lsu_tag_in}),
.req_ready_in ({tex_dcache_req_if.ready, lsu_dcache_req_if.ready}), .req_ready_in ({tex_dcache_req_if.ready, lsu_dcache_req_if.ready}),
// Dcache request // Dcache request
.req_valid_out (dcache_req_if.valid), .req_valid_out (dcache_req_if.valid),
@@ -107,8 +116,8 @@ module VX_execute #(
// Tex/LSU response // Tex/LSU response
.rsp_valid_out ({tex_dcache_rsp_if.valid, lsu_dcache_rsp_if.valid}), .rsp_valid_out ({tex_dcache_rsp_if.valid, lsu_dcache_rsp_if.valid}),
.rsp_data_out ({tex_dcache_rsp_if.data, lsu_dcache_rsp_if.data}), .rsp_data_out ({tex_dcache_rsp_if.data, lsu_dcache_rsp_if.data}),
.rsp_tag_out ({tex_dcache_rsp_if.tag, {tmp, lsu_dcache_rsp_if.tag}}), .rsp_tag_out ({tex_dcache_rsp_if.tag, lsu_tag_out}),
.rsp_ready_out ({tex_dcache_rsp_if.ready, lsu_dcache_rsp_if.ready}), .rsp_ready_out ({tex_dcache_rsp_if.ready, lsu_dcache_rsp_if.ready}),
// Dcache response // Dcache response

8
hw/rtl/interfaces/VX_dcache_core_rsp_if.v
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@@ -9,10 +9,10 @@ interface VX_dcache_core_rsp_if #(
parameter CORE_TAG_WIDTH = 1 parameter CORE_TAG_WIDTH = 1
) (); ) ();
wire [LANES-1:0] valid; wire [LANES-1:0] valid;
wire [LANES-1:0][`WORD_WIDTH-1:0]data; wire [LANES-1:0][`WORD_WIDTH-1:0] data;
wire [CORE_TAG_WIDTH-1:0] tag; wire [CORE_TAG_WIDTH-1:0] tag;
wire ready; wire ready;
endinterface endinterface

4
hw/rtl/tex_unit/VX_tex_sampler.v
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@@ -33,7 +33,7 @@ module VX_tex_sampler #(
`UNUSED_PARAM (CORE_ID) `UNUSED_PARAM (CORE_ID)
wire [31:0] req_data [`NUM_THREADS-1:0]; /*wire [31:0] req_data [`NUM_THREADS-1:0];
if (req_filter == 0) begin // point sampling if (req_filter == 0) begin // point sampling
@@ -93,6 +93,6 @@ module VX_tex_sampler #(
.enable (~stall_out), .enable (~stall_out),
.data_in ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, req_data}), .data_in ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, req_data}),
.data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data}) .data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data})
); );*/
endmodule endmodule

6
hw/rtl/tex_unit/VX_tex_unit.v
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@@ -91,7 +91,7 @@ module VX_tex_unit #(
VX_tex_addr #( VX_tex_addr #(
.REQ_INFO_WIDTH (REQ_INFO_WIDTH_A) .REQ_INFO_WIDTH (REQ_INFO_WIDTH_A)
) tex_addr ( ) _tex_addr (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -174,9 +174,9 @@ module VX_tex_unit #(
assign {rsp_format, rsp_u, rsp_v, rsp_rd, rsp_wb} = mem_rsp_info; assign {rsp_format, rsp_u, rsp_v, rsp_rd, rsp_wb} = mem_rsp_info;
VX_tex_sampler #( VX_tex_sampler #(
.CORE_ID (CORE_ID) .CORE_ID (CORE_ID)
) tex_sampler ( ) tex_sampler (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),