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Changed hierarchy + Identified private + public modules

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This commit is contained in:
felsabbagh3
2019-05-07 23:45:05 -07:00
parent 191ed73415
commit 79356c7ab1
20 changed files with 2602 additions and 694 deletions
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138
rtl/VX_decode.v
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@@ -49,10 +49,6 @@ module VX_decode(
wire[6:0] curr_opcode;
wire[31:0] rd1_register[`NT_M1:0];
wire[31:0] rd2_register[`NT_M1:0];
wire is_itype;
wire is_rtype;
wire is_stype;
@@ -107,104 +103,31 @@ module VX_decode(
reg[4:0] alu_op;
reg[4:0] mul_alu;
// wire[31:0] internal_rd1;
// wire[31:0] internal_rd2;
VX_context VX_Context(
.clk (clk),
.in_valid (in_wb_valid),
.in_rd (in_rd),
.in_src1 (out_rs1),
.in_src2 (out_rs2),
.in_curr_PC (in_curr_PC),
.in_is_clone (is_clone),
.in_is_jal (is_jal),
.in_src1_fwd (in_src1_fwd),
.in_src1_fwd_data (in_src1_fwd_data),
.in_src2_fwd (in_src2_fwd),
.in_src2_fwd_data (in_src2_fwd_data),
.in_write_register(write_register),
.in_write_data (in_write_data),
.out_a_reg_data (out_a_reg_data),
.out_b_reg_data (out_b_reg_data),
.out_clone_stall (out_clone_stall)
);
// VX_register_file vx_register_file_0(
// .clk(clk),
// .in_valid(in_wb_valid[0]),
// .in_write_register(write_register),
// .in_rd(in_rd),
// .in_data(in_write_data[1:0]),
// .in_src1(out_rs1),
// .in_src2(out_rs2),
// .out_src1_data(rd1_register),
// .out_src2_data(rd2_register)
// );
// VX_register_file vx_register_file_1(
// .clk(clk),
// .in_valid(in_wb_valid),
// .in_write_register(write_register),
// .in_rd(in_rd),
// .in_data(in_write_data),
// .in_src1(out_rs1),
// .in_src2(out_rs2),
// .out_src1_data(rd1_register),
// .out_src2_data(rd2_register)
// );
assign out_valid = in_valid;
assign write_register = (in_wb != 2'h0) ? (1'b1) : (1'b0);
// always @(*) begin
// $display("DECODE PC: %h",in_curr_PC);
// end
// always @(posedge clk) begin
// $display("Decode: curr_pc: %h", in_curr_PC);
// end
/* verilator lint_off UNUSED */
wire[31:0] clone_regsiters[31:0];
/* verilator lint_on UNUSED */
VX_register_file vx_register_file_master(
.clk (clk),
.in_valid (in_wb_valid[0]),
.in_write_register (write_register),
.in_rd (in_rd),
.in_data (in_write_data[0]),
.in_src1 (out_rs1),
.in_src2 (out_rs2),
.out_regs (clone_regsiters),
.out_src1_data (rd1_register[0]),
.out_src2_data (rd2_register[0])
);
// wire to_clone_1 = (1 == rd1_register[0]) && (state_stall == 1);
// VX_register_file_slave vx_register_file_slave(
// .clk (clk),
// .in_valid (in_wb_valid[1]),
// .in_write_register (write_register),
// .in_rd (in_rd),
// .in_data (in_write_data[1]),
// .in_src1 (out_rs1),
// .in_src2 (out_rs2),
// .in_clone (is_clone),
// .in_to_clone (to_clone_1),
// .in_regs (clone_regsiters),
// .out_src1_data (rd1_register[1]),
// .out_src2_data (rd2_register[1])
// );
genvar index;
generate
for (index=1; index < `NT; index=index+1)
begin: gen_code_label
wire to_clone;
assign to_clone = (index == rd1_register[0]) && (state_stall == 1);
VX_register_file_slave vx_register_file_slave(
.clk (clk),
.in_valid (in_wb_valid[index]),
.in_write_register (write_register),
.in_rd (in_rd),
.in_data (in_write_data[index]),
.in_src1 (out_rs1),
.in_src2 (out_rs2),
.in_clone (is_clone),
.in_to_clone (to_clone),
.in_regs (clone_regsiters),
.out_src1_data (rd1_register[index]),
.out_src2_data (rd2_register[index])
);
end
endgenerate
assign curr_opcode = in_instruction[6:0];
@@ -278,32 +201,11 @@ module VX_decode(
// $display("Decode inst: %h", in_instruction);
// end
reg[5:0] state_stall = 0;
always @(posedge clk) begin
if ((is_clone) && state_stall == 0) begin
state_stall <= 10;
// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, is_clone);
end else if (state_stall == 1) begin
// $display("ENDING CLONE, 1 =? %h = %h -- %d", rd1_register[0], to_clone_1, is_clone);
state_stall <= 0;
end else if (state_stall > 0) begin
state_stall <= state_stall - 1;
// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", state_stall, rd1_register[0], to_clone_1, is_clone);
end
end
assign out_clone_stall = ((state_stall == 0) && is_clone) || ((state_stall != 1) && is_clone);
// ch_print("DECODE: PC: {0}, INSTRUCTION: {1}", in_curr_PC, in_instruction);
genvar index_out_reg;
generate
for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
begin
assign out_a_reg_data[index_out_reg] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg]));
assign out_b_reg_data[index_out_reg] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg];
end
endgenerate
// assign out_reg_data[0] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[0] : rd1_register[0]));
// assign out_reg_data[1] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[0] : rd2_register[0];