From 7863175233a02ea4f8462dc7c7df69e8854d52c7 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Wed, 30 Oct 2019 14:57:20 -0400 Subject: [PATCH] Set associative bank working --- kernel/vortex_test.elf | Bin 15724 -> 15724 bytes kernel/vx_os/vx_back/vx_back.s | 26 +++--- rtl/VX_dmem_controller.v | 4 + rtl/cache/VX_Cache_Bank.v | 82 +++++++++++++----- rtl/cache/VX_cache_data.v | 46 +++++----- rtl/cache/VX_cache_data_per_index.v | 125 ++++++++++++++++++++++++++++ rtl/cache/VX_d_cache.v | 16 +++- rtl/modelsim/Makefile | 3 +- rtl/modelsim/vortex_dpi.cpp | 3 + syn/fsyn.tcl | 2 +- syn/syn.tcl | 2 +- 11 files changed, 242 insertions(+), 67 deletions(-) create mode 100644 rtl/cache/VX_cache_data_per_index.v diff --git a/kernel/vortex_test.elf b/kernel/vortex_test.elf index f3408690e57ef4e7ccebd4a54d9caf191cea69bd..df2ef62c28268a3215bd779805baf0f19931ec34 100755 GIT binary patch delta 41 xcmaD;^`>frsRf(4ms>?}*<@>rMz+W>*C?OL$%iZg*mBcL98+>OOIU`m003I84=?}# delta 41 xcmaD;^`>frsRdhxX_0|>=45M&MmBGcY?A_?$%iZg*u2cljDlP?OIU`m002ya4hH}L diff --git a/kernel/vx_os/vx_back/vx_back.s b/kernel/vx_os/vx_back/vx_back.s index 1ff8b571..1afae6d3 100644 --- a/kernel/vx_os/vx_back/vx_back.s +++ b/kernel/vx_os/vx_back/vx_back.s @@ -15,26 +15,22 @@ _start: # li a1, 7 # sw a1, 0(a0) - # # la a0, 0x10000048 - # # li a1, 3 - # # sw a1, 0(a0) + # la a0, 0x10000048 + # li a1, 3 + # sw a1, 0(a0) - # # la a0, 0x80000000 - # # li a1, 9 - # # sw a1, 0(a0) + # la a0, 0x80000000 + # li a1, 9 + # sw a1, 0(a0) - # # la a0, 0x80000008 - # # li a1, 8 - # # sw a1, 0(a0) + # la a0, 0x80000008 + # li a1, 8 + # sw a1, 0(a0) # la a0, 0x10000000 # lw a2, 0(a0) - # # la a0, 0x10000048 - # # lw a3, 0(a0) - # # la a0, 0x00000000 # I=0,OF=0, B=0 - # # li a1, 1 - # # sw a1, 0(a0) - # # lw a2, 0(a0) + # la a0, 0x10000048 + # lw a3, 0(a0) # li a0, 0 # .word 0x0005006b # tmc a0 ######################################## diff --git a/rtl/VX_dmem_controller.v b/rtl/VX_dmem_controller.v index 258a7b6f..49bf941c 100644 --- a/rtl/VX_dmem_controller.v +++ b/rtl/VX_dmem_controller.v @@ -54,7 +54,11 @@ module VX_dmem_controller ( VX_d_cache #( .CACHE_SIZE(4096), // Bytes + `ifdef SYN .CACHE_WAYS(1), + `else + .CACHE_WAYS(4), + `endif .CACHE_BLOCK(128), // Bytes .CACHE_BANKS(8), .NUM_REQ(`NT) diff --git a/rtl/cache/VX_Cache_Bank.v b/rtl/cache/VX_Cache_Bank.v index 1d53486f..5753c7d0 100644 --- a/rtl/cache/VX_Cache_Bank.v +++ b/rtl/cache/VX_Cache_Bank.v @@ -18,8 +18,8 @@ module VX_Cache_Bank rst, state, read_or_write, // Read = 0 | Write = 1 - i_p_mem_read, - i_p_mem_write, + i_p_mem_read, + i_p_mem_write, valid_in, //write_from_mem, actual_index, @@ -37,7 +37,9 @@ module VX_Cache_Bank eviction_wb, // Need to evict eviction_addr, // What's the eviction tag - data_evicted + data_evicted, + evicted_way, + way_use ); localparam NUMBER_BANKS = CACHE_BANKS; @@ -72,6 +74,10 @@ module VX_Cache_Bank input wire[2:0] i_p_mem_write; input wire[1:0] byte_select; + + input wire[$clog2(CACHE_WAYS)-1:0] evicted_way; + output wire[$clog2(CACHE_WAYS)-1:0] way_use; + // Outputs // Normal shit output wire[31:0] readdata; @@ -88,8 +94,8 @@ module VX_Cache_Bank wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use; - wire[16:0] tag_use; - wire[16:0] eviction_tag; + wire[`CACHE_TAG_SIZE_RNG] tag_use; + wire[`CACHE_TAG_SIZE_RNG] eviction_tag; wire valid_use; wire dirty_use; wire access; @@ -97,19 +103,23 @@ module VX_Cache_Bank wire miss; // -10/21 + + wire[$clog2(CACHE_WAYS)-1:0] update_way; + wire[$clog2(CACHE_WAYS)-1:0] way_to_update; + assign miss = (tag_use != o_tag) && valid_use && valid_in; assign data_evicted = data_use; - assign eviction_wb = (dirty_use != 1'b0) && valid_use; - assign eviction_tag = tag_use; - assign access = (state == CACHE_IDLE) && valid_in; + assign eviction_wb = miss && (dirty_use != 1'b0) && valid_use; + assign eviction_tag = tag_use; + assign access = (state == CACHE_IDLE) && valid_in; assign write_from_mem = (state == RECIV_MEM_RSP) && valid_in; // TODO - assign hit = (access && (tag_use == o_tag) && valid_use); + assign hit = (access && (tag_use == o_tag) && valid_use); //assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data - assign eviction_addr = {eviction_tag, actual_index, 7'b0}; // Fix with actual data - + assign eviction_addr = {eviction_tag, actual_index, 7'b0}; // Fix with actual data + assign update_way = hit ? way_use : 0; @@ -168,29 +178,55 @@ module VX_Cache_Bank // assign we[g] = (normal_write || (write_from_mem)) ? 1'b1 : 1'b0; assign data_write[g] = write_from_mem ? fetched_writedata[g] : writedata; + assign way_to_update = write_from_mem ? evicted_way : update_way; end - VX_cache_data #( + + VX_cache_data_per_index #( .CACHE_SIZE(CACHE_SIZE), .CACHE_WAYS(CACHE_WAYS), .CACHE_BLOCK(CACHE_BLOCK), .CACHE_BANKS(CACHE_BANKS), .NUM_WORDS_PER_BLOCK(NUM_WORDS_PER_BLOCK)) data_structures( - .clk (clk), - .rst (rst), + .clk (clk), + .rst (rst), + .valid_in (valid_in), // Inputs - .addr (actual_index), - .we (we), - .evict (write_from_mem), - .data_write(data_write), - .tag_write (o_tag), + .addr (actual_index), + .we (we), + .evict (write_from_mem), + .data_write (data_write), + .tag_write (o_tag), + .way_to_update(way_to_update), // Outputs - .tag_use (tag_use), - .data_use (data_use), - .valid_use (valid_use), - .dirty_use (dirty_use) + .tag_use (tag_use), + .data_use (data_use), + .valid_use (valid_use), + .dirty_use (dirty_use), + .way (way_use) ); + // VX_cache_data #( + // .CACHE_SIZE(CACHE_SIZE), + // .CACHE_WAYS(CACHE_WAYS), + // .CACHE_BLOCK(CACHE_BLOCK), + // .CACHE_BANKS(CACHE_BANKS), + // .NUM_WORDS_PER_BLOCK(NUM_WORDS_PER_BLOCK)) data_structures( + // .clk (clk), + // .rst (rst), + // // Inputs + // .addr (actual_index), + // .we (we), + // .evict (write_from_mem), + // .data_write(data_write), + // .tag_write (o_tag), + // // Outputs + // .tag_use (tag_use), + // .data_use (data_use), + // .valid_use (valid_use), + // .dirty_use (dirty_use) + // ); + endmodule diff --git a/rtl/cache/VX_cache_data.v b/rtl/cache/VX_cache_data.v index cfbd02d7..67fdc4a5 100644 --- a/rtl/cache/VX_cache_data.v +++ b/rtl/cache/VX_cache_data.v @@ -13,37 +13,37 @@ module VX_cache_data ( input wire clk, rst, // Clock - `ifdef PARAM + // `ifdef PARAM // Addr - input wire[`CACHE_IND_SIZE_RNG] addr, + input wire[`CACHE_IND_SIZE_RNG] addr, // WE - input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, - input wire evict, + input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, + input wire evict, // Data - input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, - input wire[`CACHE_TAG_SIZE_RNG] tag_write, + input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, + input wire[`CACHE_TAG_SIZE_RNG] tag_write, output wire[`CACHE_TAG_SIZE_RNG] tag_use, output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, output wire valid_use, output wire dirty_use - `else - // Addr - input wire[7:0] addr, - // WE - input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, - input wire evict, - // Data - input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data - input wire[16:0] tag_write, + // `else + // // Addr + // input wire[7:0] addr, + // // WE + // input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, + // input wire evict, + // // Data + // input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data + // input wire[16:0] tag_write, - output wire[16:0] tag_use, - output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, - output wire valid_use, - output wire dirty_use - `endif + // output wire[16:0] tag_use, + // output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, + // output wire valid_use, + // output wire dirty_use + // `endif ); @@ -62,9 +62,9 @@ module VX_cache_data // (3:0) 4 bytes reg[NUM_WORDS_PER_BLOCK-1:0][3:0][7:0] data[NUMBER_INDEXES-1:0]; // Actual Data - reg[16:0] tag[NUMBER_INDEXES-1:0]; - reg valid[NUMBER_INDEXES-1:0]; - reg dirty[NUMBER_INDEXES-1:0]; + reg[`CACHE_TAG_SIZE_RNG] tag[NUMBER_INDEXES-1:0]; + reg valid[NUMBER_INDEXES-1:0]; + reg dirty[NUMBER_INDEXES-1:0]; // 16 bytes diff --git a/rtl/cache/VX_cache_data_per_index.v b/rtl/cache/VX_cache_data_per_index.v new file mode 100644 index 00000000..2a4b2e77 --- /dev/null +++ b/rtl/cache/VX_cache_data_per_index.v @@ -0,0 +1,125 @@ + + +`include "../VX_define.v" + +module VX_cache_data_per_index + #( + parameter CACHE_SIZE = 4096, // Bytes + parameter CACHE_WAYS = 1, + parameter CACHE_BLOCK = 128, // Bytes + parameter CACHE_BANKS = 8, + parameter NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4) + ) + ( + input wire clk, // Clock + input wire rst, + input wire valid_in, + // Addr + input wire[`CACHE_IND_SIZE_RNG] addr, + // WE + input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we, + input wire evict, + input wire[$clog2(CACHE_WAYS)-1:0] way_to_update, + // Data + input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data + input wire[`CACHE_TAG_SIZE_RNG] tag_write, + + + output wire[`CACHE_TAG_SIZE_RNG] tag_use, + output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use, + output wire valid_use, + output wire dirty_use, + output wire[$clog2(CACHE_WAYS)-1:0] way + +); + localparam NUMBER_BANKS = CACHE_BANKS; + localparam CACHE_BLOCK_PER_BANK = (CACHE_BLOCK / CACHE_BANKS); + // localparam NUM_WORDS_PER_BLOCK = CACHE_BLOCK / (CACHE_BANKS*4); + localparam NUMBER_INDEXES = `NUM_IND; + + wire [CACHE_WAYS-1:0][`CACHE_TAG_SIZE_RNG] tag_use_per_way; + wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_use_per_way; + wire [CACHE_WAYS-1:0] valid_use_per_way; + wire [CACHE_WAYS-1:0] dirty_use_per_way; + wire [CACHE_WAYS-1:0] hit_per_way; + reg [NUMBER_INDEXES-1:0][$clog2(CACHE_WAYS)-1:0] eviction_way_index; + wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way; + wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way; + wire [CACHE_WAYS-1:0] write_from_mem_per_way; + wire invalid_found; + + wire [$clog2(CACHE_WAYS)-1:0] way_index; + wire [$clog2(CACHE_WAYS)-1:0] invalid_index; + VX_generic_priority_encoder #(.N(CACHE_WAYS)) valid_index + ( + .valids(~valid_use_per_way), + .index (invalid_index), + .found (invalid_found) + ); + + VX_generic_priority_encoder #(.N(CACHE_WAYS)) way_indexing + ( + .valids(hit_per_way), + .index (way_index), + .found () + ); + + + + wire hit = |hit_per_way && valid_in; + wire miss = ~hit && valid_in; + wire update = |we && valid_in && !miss; + wire valid = &valid_use_per_way && valid_in; + + assign way = hit ? way_index : (valid ? eviction_way_index[addr] : (invalid_found ? invalid_index : 0)); + assign tag_use = hit ? tag_use_per_way[way_index] : (valid ? tag_use_per_way[eviction_way_index[addr]] : (invalid_found ? tag_use_per_way[invalid_index] : 0)); + assign data_use = hit ? data_use_per_way[way_index] : (valid ? data_use_per_way[eviction_way_index[addr]] : (invalid_found ? data_use_per_way[invalid_index] : 0)); + assign valid_use = hit ? valid_use_per_way[way_index] : (valid ? valid_use_per_way[eviction_way_index[addr]] : (invalid_found ? valid_use_per_way[invalid_index] : 0)); + assign dirty_use = hit ? dirty_use_per_way[way_index] : (valid ? dirty_use_per_way[eviction_way_index[addr]] : (invalid_found ? dirty_use_per_way[invalid_index] : 0)); + + + + genvar ways; + for(ways=0; ways < CACHE_WAYS; ways = ways + 1) begin + + assign hit_per_way[ways] = ((valid_use_per_way[ways] == 1'b1) && (tag_use_per_way[ways] == tag_write)) ? 1'b1 : 0; + assign we_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? (we) : 0) : 0; + assign data_write_per_way[ways] = (evict == 1'b1) || (update == 1'b1) ? ((ways == way_to_update) ? data_write : 0) : 0; + assign write_from_mem_per_way[ways] = (evict == 1'b1) ? ((ways == way_to_update) ? 1 : 0) : 0; + + VX_cache_data #( + .CACHE_SIZE(CACHE_SIZE), + .CACHE_WAYS(CACHE_WAYS), + .CACHE_BLOCK(CACHE_BLOCK), + .CACHE_BANKS(CACHE_BANKS)) data_structures( + .clk (clk), + .rst (rst), + // Inputs + .addr (addr), + .we (we_per_way[ways]), + .evict (write_from_mem_per_way[ways]), + .data_write(data_write_per_way[ways]), + .tag_write (tag_write), + // Outputs + .tag_use (tag_use_per_way[ways]), + .data_use (data_use_per_way[ways]), + .valid_use (valid_use_per_way[ways]), + .dirty_use (dirty_use_per_way[ways]) + ); + end + + always @(posedge clk or posedge rst) begin + if (rst) begin + eviction_way_index <= 0; + end else begin + if(miss && dirty_use && valid_use && !evict && valid_in) begin // can be either evict or invalid cache entries + if((eviction_way_index[addr]+1) == CACHE_WAYS) begin + eviction_way_index[addr] <= 0; + end else begin + eviction_way_index[addr] <= (eviction_way_index[addr] + 1); + end + end + end + end + +endmodule \ No newline at end of file diff --git a/rtl/cache/VX_d_cache.v b/rtl/cache/VX_d_cache.v index d1893dba..1bf09ede 100644 --- a/rtl/cache/VX_d_cache.v +++ b/rtl/cache/VX_d_cache.v @@ -96,6 +96,11 @@ module VX_d_cache wire[NUMBER_BANKS-1:0] hit_per_bank; // Whether each bank got a hit or a miss wire[NUMBER_BANKS-1:0] eviction_wb; + + wire[NUMBER_BANKS -1 : 0][$clog2(CACHE_WAYS)-1:0] evicted_way_new; + reg [NUMBER_BANKS -1 : 0][$clog2(CACHE_WAYS)-1:0] evicted_way_old; + wire[NUMBER_BANKS -1 : 0][$clog2(CACHE_WAYS)-1:0] way_used; + // Internal State reg [3:0] state; wire[3:0] new_state; @@ -230,6 +235,7 @@ module VX_d_cache // begin // debug_hit_per_bank_mask[init_b] <= 0; // end + evicted_way_old <= 0; end else begin state <= new_state; @@ -242,6 +248,7 @@ module VX_d_cache end final_data_read <= new_final_data_read_Qual; + evicted_way_old <= evicted_way_new; end end @@ -254,6 +261,9 @@ module VX_d_cache (state == RECIV_MEM_RSP) ? miss_addr : i_p_addr[send_index_to_bank[bank_id]]; + assign evicted_way_new[bank_id] = (state == SEND_MEM_REQ) ? way_used[bank_id] : + (state == RECIV_MEM_RSP) ? evicted_way_old[bank_id] : + 0; wire[1:0] byte_select = bank_addr[1:0]; wire[`CACHE_OFFSET_SIZE_RNG] cache_offset = bank_addr[`CACHE_ADDR_OFFSET_RNG]; @@ -290,9 +300,9 @@ module VX_d_cache .eviction_addr (eviction_addr_per_bank[bank_id]), .data_evicted (o_m_writedata[bank_id]), .eviction_wb (eviction_wb[bank_id]), // Something needs to be written back - - - .fetched_writedata(i_m_readdata[bank_id]) // Data From memory + .fetched_writedata(i_m_readdata[bank_id]), // Data From memory + .evicted_way (evicted_way_new[bank_id]), + .way_use (way_used[bank_id]) ); end diff --git a/rtl/modelsim/Makefile b/rtl/modelsim/Makefile index b6eb9776..a6b7bafb 100644 --- a/rtl/modelsim/Makefile +++ b/rtl/modelsim/Makefile @@ -68,6 +68,7 @@ SRC = \ ../cache/VX_d_cache.v \ ../cache/VX_generic_pe.v \ ../cache/cache_set.v \ +../cache/VX_cache_data_per_index.v \ ../pipe_regs/VX_d_e_reg.v \ ../pipe_regs/VX_f_d_reg.v \ ../shared_memory/VX_bank_valids.v \ @@ -103,7 +104,7 @@ LOG= # vlib comp: - vlog -O0 $(OPT) -work $(LIB) $(SRC) + vlog $(OPT) -work $(LIB) $(SRC) # vlog -O0 -dpiheader vortex_dpi.h $(OPT) -work $(LIB) $(SRC) diff --git a/rtl/modelsim/vortex_dpi.cpp b/rtl/modelsim/vortex_dpi.cpp index 75801872..c9444de3 100644 --- a/rtl/modelsim/vortex_dpi.cpp +++ b/rtl/modelsim/vortex_dpi.cpp @@ -24,6 +24,7 @@ RAM ram; bool refill; unsigned refill_addr; +unsigned num_cycles; unsigned getIndex(int, int, int); unsigned getIndex(int r, int c, int numCols) @@ -48,6 +49,7 @@ void ibus_driver(bool clk, unsigned pc_addr, unsigned * instruction) // printf("Inside ibus_driver\n"); if (clk) { + num_cycles++; (*instruction) = 0; } else @@ -199,6 +201,7 @@ void io_handler(bool clk, bool io_valid, unsigned io_data) void gracefulExit() { + fprintf(stderr, "Num Cycles: %d\n", num_cycles); fprintf(stderr, "\n*********************\n\n"); } diff --git a/syn/fsyn.tcl b/syn/fsyn.tcl index 22d32e53..87a95370 100644 --- a/syn/fsyn.tcl +++ b/syn/fsyn.tcl @@ -2,7 +2,7 @@ set search_path [concat ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shar set link_library [concat NanGate_15nm_OCL.db] set symbol_library {} set target_library [concat NanGate_15nm_OCL.db] -set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \ +set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \ ] # set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \ # ] diff --git a/syn/syn.tcl b/syn/syn.tcl index 78afadf0..0c5046ab 100755 --- a/syn/syn.tcl +++ b/syn/syn.tcl @@ -3,7 +3,7 @@ set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_ set symbol_library {} set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db] -set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \ +set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \ ] # set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \ # ]