Updated TODO

2019-03-22 04:21:21 -04:00
parent 6c64fa35f8
commit 781c11c93f
13 changed files with 2 additions and 40 deletions
--- a/3
+++ b/3
@@ -2,4 +2,5 @@


 * csri bug?
-* Start on the Verilog Pipeline (Research loading into mem)
+* Add hardware threads to rtl
+* Add hardware warps to rtl