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optimized opae cci to dev memcpy using double buffering and request window to work around unordered read requests

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This commit is contained in:
Blaise Tine
2020-04-23 01:30:45 -07:00
parent 3e64cb4380
commit 77a52ea20b
10 changed files with 249 additions and 110 deletions
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7
hw/rtl/VX_define.vh
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@@ -29,7 +29,12 @@
if (!(cond)) $error(msg); \
endgenerate
`define LOG2UP(x) ((x > 1) ? $clog2(x) : 1)
`define CLOG2(x) $clog2(x);
`define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > x) ? 1 : 0))
`define LOG2UP(x) ((x > 1) ? $clog2(x) : 1)
`define MIN(x, y) ((x < y) ? x : y);
`define MAX(x, y) ((x > y) ? x : y);
///////////////////////////////////////////////////////////////////////////////

9
hw/rtl/Vortex.v
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@@ -43,6 +43,15 @@ module Vortex #(
input wire [31:0] llc_snp_req_addr,
output wire llc_snp_req_ready,
// CSR request
//input wire csr_read_valid;
//input wire csr_write_valid;
//input wire [`CSR_WIDTH-1:0 csr_index;
//input wire csr_data_in;
//output wire [15:0] csr_data_out;
output wire ebreak
);
`DEBUG_BEGIN

30
hw/rtl/libs/VX_generic_queue.v
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@@ -10,16 +10,16 @@ module VX_generic_queue #(
input wire push,
input wire pop,
output wire empty,
output wire full,
output wire full,
`IGNORE_WARNINGS_END
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out
);
if (SIZE == 0) begin
assign empty = 1;
assign data_out = data_in;
assign full = 0;
assign empty = 1;
assign data_out = data_in;
assign full = 0;
end else begin // (SIZE > 0)
@@ -56,10 +56,9 @@ module VX_generic_queue #(
end
end
assign data_out = head_r;
assign empty = (size_r == 0);
assign full = (size_r != 0) && !pop;
assign data_out = head_r;
assign empty = (size_r == 0);
assign full = (size_r != 0);
end else begin // (SIZE > 1)
reg [DATAW-1:0] curr_r;
@@ -82,18 +81,21 @@ module VX_generic_queue #(
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
empty_r <= 1;
empty_r <= 1;
full_r <= 0;
end else begin
if (writing && !reading) begin
size_r <= size_r + 1;
empty_r <= 0;
if (size_r == SIZE-1)
if (size_r == SIZE-1) begin
full_r <= 1;
end else if (reading && !writing) begin
end
end else
if (reading && !writing) begin
size_r <= size_r - 1;
if (size_r == 1)
empty_r <= 1;
if (size_r == 1) begin
empty_r <= 1;
end;
full_r <= 0;
end
end
@@ -133,5 +135,5 @@ module VX_generic_queue #(
assign full = full_r;
end
end
endmodule

19
hw/rtl/tex_unit/VX_tex_mgr.v Normal file
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@@ -0,0 +1,19 @@
`include "VX_define.vh"
module VX_tex_mgr (
input wire clk,
input wire reset,
);
//--
endmodule

50
hw/rtl/tex_unit/VX_tex_unit.v Normal file
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@@ -0,0 +1,50 @@
`include "VX_define.vh"
module VX_tex_unit #(
parameter TADDRW = 32,
parameter MADDRW = 32,
parameter DATAW = 32,
parameter MAXWTW = 8,
parameter MAXHTW = 8,
parameter MAXFTW = 2,
parameter MAXFMW = 1,
parameter MAXAMW = 2,
parameter TAGW = 16,
parameter NUMCRQS = 32,
) (
input wire clk,
input wire reset,
// Texture Request
input wire tex_req_valid,
input wire [TADDRW-1:0] tex_req_u,
input wire [TADDRW-1:0] tex_req_v,
input wire [MADDRW-1:0] tex_req_addr,
input wire [MAXWTW-1:0] tex_req_width,
input wire [MAXHTW-1:0] tex_req_height,
input wire [MAXFTW-1:0] tex_req_format,
input wire [MAXFMW-1:0] tex_req_filter,
input wire [MAXAMW-1:0] tex_req_clamp,
input wire [TAGW-1:0] tex_req_tag,
output wire tex_req_ready,
// Texture Response
output wire tex_rsp_valid,
output wire [TAGW-1:0] tex_rsp_tag,
input wire [DATAW-1:0] tex_rsp_data,
input wire tex_rsp_ready,
// Cache Request
output wire [NUMCRQS-1:0] cache_req_valids,
output wire [NUMCRQS-1:0][MADDRW-1:0] cache_req_addrs,
input wire cache_req_ready,
// Cache Response
input wire cache_rsp_valid,
input wire [MADDRW-1:0] cache_rsp_addr,
input wire [DATAW-1:0] cache_rsp_data,
output wire cache_rsp_ready
);
endmodule