cache bank refactoring - removing unecessary core response fifo & restoring single port data access
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@@ -212,7 +212,7 @@
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"miss_st0": 1,
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"force_miss_st0": 1,
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"mshr_push": 1,
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"?crsq_alm_full": 1,
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"?crsq_in_stall": 1,
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"?dreq_alm_full": 1,
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"?mshr_alm_full": 1
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}
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