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cache bank refactoring - removing unecessary core response fifo & restoring single port data access

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This commit is contained in:
Blaise Tine
2021-02-21 21:47:46 -08:00
parent ccb74ef286
commit 7560202f8b
12 changed files with 129 additions and 294 deletions
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4
hw/rtl/cache/VX_cache.v vendored
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@@ -23,9 +23,6 @@ module VX_cache #(
parameter MSHR_SIZE = 16,
// DRAM Response Queue Size
parameter DRSQ_SIZE = 4,
// Core Response Queue Size
parameter CRSQ_SIZE = 4,
// DRAM Request Queue Size
parameter DREQ_SIZE = 4,
@@ -298,7 +295,6 @@ module VX_cache #(
.CREQ_SIZE (CREQ_SIZE),
.MSHR_SIZE (MSHR_SIZE),
.DRSQ_SIZE (DRSQ_SIZE),
.CRSQ_SIZE (CRSQ_SIZE),
.DREQ_SIZE (DREQ_SIZE),
.WRITE_ENABLE (WRITE_ENABLE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),