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cache bank refactoring - removing unecessary core response fifo & restoring single port data access

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Blaise Tine
2021-02-21 21:47:46 -08:00
parent ccb74ef286
commit 7560202f8b
12 changed files with 129 additions and 294 deletions
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hw/rtl/VX_scope.vh
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@@ -7,7 +7,7 @@
`define SCOPE_ASSIGN(d,s) assign scope_``d = s
`define SCOPE_SIZE 16384
`define SCOPE_SIZE 4096
`else