cache bank refactoring - removing unecessary core response fifo & restoring single port data access

2021-02-21 21:47:46 -08:00
parent ccb74ef286
commit 7560202f8b
12 changed files with 129 additions and 294 deletions
--- a/hw/rtl/VX_cluster.v
+++ b/hw/rtl/VX_cluster.v
@@ -170,7 +170,6 @@ module VX_cluster #(
            .CREQ_SIZE          (`L2CREQ_SIZE),
            .MSHR_SIZE          (`L2MSHR_SIZE),
            .DRSQ_SIZE          (`L2DRSQ_SIZE),
-            .CRSQ_SIZE          (`L2CRSQ_SIZE),
            .DREQ_SIZE          (`L2DREQ_SIZE),
            .WRITE_ENABLE       (1),          
            .CORE_TAG_WIDTH     (`XDRAM_TAG_WIDTH),