diff --git a/hw/rtl/VX_csr_io_arb.v b/hw/rtl/VX_csr_io_arb.v index b45250e9..e8714bf0 100644 --- a/hw/rtl/VX_csr_io_arb.v +++ b/hw/rtl/VX_csr_io_arb.v @@ -73,7 +73,7 @@ module VX_csr_io_arb #( .flush (1'b0), .in ({csr_io_rsp_valid_in[rsp_idx], csr_io_rsp_data_in[rsp_idx]}), .out ({csr_io_rsp_valid_out, csr_io_rsp_data_out}) - ); + ); for (genvar i = 0; i < NUM_REQUESTS; i++) begin assign csr_io_rsp_ready_in[i] = rsp_1hot[i] && ~stall; diff --git a/hw/rtl/VX_csr_unit.v b/hw/rtl/VX_csr_unit.v index 6b1c19b4..baaab4e3 100644 --- a/hw/rtl/VX_csr_unit.v +++ b/hw/rtl/VX_csr_unit.v @@ -63,11 +63,11 @@ module VX_csr_unit #( .busy (busy) ); - wire csr_hazard = (csr_addr_s1 == csr_pipe_req_if.csr_addr) - && (csr_pipe_rsp_if.wid == csr_pipe_req_if.wid) - && csr_pipe_rsp_if.valid; + wire write_hazard = (csr_addr_s1 == csr_pipe_req_if.csr_addr) + && (csr_pipe_rsp_if.wid == csr_pipe_req_if.wid) + && csr_pipe_rsp_if.valid; - wire [31:0] csr_read_data_qual = csr_hazard ? csr_updated_data_s1 : csr_read_data; + wire [31:0] csr_read_data_qual = write_hazard ? csr_updated_data_s1 : csr_read_data; reg [31:0] csr_updated_data; @@ -88,7 +88,7 @@ module VX_csr_unit #( csr_updated_data = csr_read_data_qual & (32'hFFFFFFFF - csr_pipe_req_if.csr_mask); csr_we_s0_unqual = (csr_pipe_req_if.csr_mask != 0); end - default: csr_updated_data = 32'hdeadbeef; + default: csr_updated_data = 'x; endcase end diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index 8e0ba8ae..9683c8f8 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -79,7 +79,7 @@ module VX_decode #( `INST_L, `INST_FL: src2_imm = {{20{u_12[11]}}, u_12}; `INST_B: src2_imm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0}; - default: src2_imm = 32'hdeadbeef; + default: src2_imm = 'x; endcase end