From 72e06ef4fe740269e032430f0dc4d36be385a02f Mon Sep 17 00:00:00 2001
From: Krishna Yalamarthy <kyalamarthy6@boson.cc.gt.atl.ga.us>
Date: Sat, 13 Mar 2021 22:01:25 -0500
Subject: [PATCH] Tex CSRs write support added

---
 driver/tests/tex_demo/common.h    |   2 +
 driver/tests/tex_demo/demo        | Bin 48680 -> 48696 bytes
 driver/tests/tex_demo/demo.cpp    |   1 +
 driver/tests/tex_demo/kernel.c    |   4 +-
 hw/VX_config.h                    |  29 ++++++++++++-
 hw/rtl/VX_config.vh               |  25 +++++++++++
 hw/rtl/VX_csr_data.v              |   8 +++-
 hw/rtl/VX_csr_unit.v              |   4 +-
 hw/rtl/VX_define.vh               |   1 +
 hw/rtl/VX_execute.v               |   6 ++-
 hw/rtl/VX_gpu_unit.v              |   2 +
 hw/rtl/interfaces/VX_tex_csr_if.v |  20 +++++++++
 hw/rtl/interfaces/VX_tex_req_if.v |   1 +
 hw/rtl/tex_unit/VX_tex_unit.v     |  70 +++++++++++++++++++++++++++++-
 14 files changed, 166 insertions(+), 7 deletions(-)
 create mode 100644 hw/rtl/interfaces/VX_tex_csr_if.v

diff --git a/driver/tests/tex_demo/common.h b/driver/tests/tex_demo/common.h
index d6540ae1..d24a889c 100644
--- a/driver/tests/tex_demo/common.h
+++ b/driver/tests/tex_demo/common.h
@@ -3,6 +3,8 @@
 
 #define KERNEL_ARG_DEV_MEM_ADDR 0x7ffff000
 
+// #include <vortex.h>
+
 struct kernel_arg_t {
   uint32_t num_tasks;
   uint32_t task_size;
diff --git a/driver/tests/tex_demo/demo b/driver/tests/tex_demo/demo
index faa176c1f1f99c50b1aa190529c615f7f604ba98..922905c550b4e28bf17d96db10408ae0bb1461bc 100755
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diff --git a/driver/tests/tex_demo/demo.cpp b/driver/tests/tex_demo/demo.cpp
index a28d675d..229734a5 100644
--- a/driver/tests/tex_demo/demo.cpp
+++ b/driver/tests/tex_demo/demo.cpp
@@ -141,6 +141,7 @@ int main(int argc, char *argv[]) {
 
   kernel_arg.num_tasks = num_tasks;
   kernel_arg.task_size = count;
+  kernel_arg.device_ptr = device;
 
   std::cout << "dev_src0=" << std::hex << kernel_arg.src0_ptr << std::endl;
   std::cout << "dev_src1=" << std::hex << kernel_arg.src1_ptr << std::endl;
diff --git a/driver/tests/tex_demo/kernel.c b/driver/tests/tex_demo/kernel.c
index c142eefb..9a936c1d 100644
--- a/driver/tests/tex_demo/kernel.c
+++ b/driver/tests/tex_demo/kernel.c
@@ -14,7 +14,9 @@ void kernel_body(int task_id, void* arg) {
 	unsigned u = 1;
 	unsigned v = 1;
 	unsigned t = 1;
-	
+
+	// vx_csr_set(_arg->device_ptr, 0, 0xfd0, 0xffd);
+
 	uint32_t offset = task_id * count;
 
 	for (uint32_t i = 0; i < count; ++i) {
diff --git a/hw/VX_config.h b/hw/VX_config.h
index f967463e..05339ece 100644
--- a/hw/VX_config.h
+++ b/hw/VX_config.h
@@ -1,5 +1,5 @@
 // auto-generated by gen_config.py. DO NOT EDIT
-// Generated at 2021-03-12 17:51:37.263369
+// Generated at 2021-03-13 13:57:30.622905
 
 #ifndef VX_USER_CONFIG
 #define VX_USER_CONFIG
@@ -7,7 +7,7 @@
 
 #endif
 // auto-generated by gen_config.py. DO NOT EDIT
-// Generated at 2021-03-12 17:51:37.265050
+// Generated at 2021-03-13 13:57:30.624676
 
 // Translated from VX_config.vh:
 
@@ -246,6 +246,31 @@
 #define CSR_NW          0xFC1
 #define CSR_NC          0xFC2
 
+////////// Texture Unit CSRs /////////////
+#define CSR_TEX_BEGIN   0xFD0
+// Unit 1
+#define CSR_TEX0_ADDR    CSR_TEX_BEGIN
+#define CSR_TEX0_FORMAT  CSR_TEX_BEGIN + 0x1
+#define CSR_TEX0_WIDTH   CSR_TEX_BEGIN + 0x2
+#define CSR_TEX0_HEIGHT  CSR_TEX_BEGIN + 0x3
+#define CSR_TEX0_STRIDE  CSR_TEX_BEGIN + 0x4
+#define CSR_TEX0_WRAP_U  CSR_TEX_BEGIN + 0x5
+#define CSR_TEX0_WRAP_V  CSR_TEX_BEGIN + 0x6
+#define CSR_TEX0_MIN_FILTER  CSR_TEX_BEGIN + 0x7
+#define CSR_TEX0_MAX_FILTER  CSR_TEX_BEGIN + 0x8
+
+// Unit 2
+#define CSR_TEX1_ADDR    CSR_TEX_BEGIN + 0x9
+#define CSR_TEX1_FORMAT  CSR_TEX_BEGIN + 0xA
+#define CSR_TEX1_WIDTH   CSR_TEX_BEGIN + 0xB
+#define CSR_TEX1_HEIGHT  CSR_TEX_BEGIN + 0xC
+#define CSR_TEX1_STRIDE  CSR_TEX_BEGIN + 0xD
+#define CSR_TEX1_WRAP_U  CSR_TEX_BEGIN + 0xE
+#define CSR_TEX1_WRAP_V  CSR_TEX_BEGIN + 0xF
+#define CSR_TEX1_MIN_FILTER  CSR_TEX_BEGIN + 0x10
+#define CSR_TEX1_MAX_FILTER  CSR_TEX_BEGIN + 0x11
+
+#define CSR_TEX_END CSR_TEX1_MAX_FILTER
 // Pipeline Queues ////////////////////////////////////////////////////////////
 
 // Size of LSU Request Queue
diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh
index ae09cdc0..fa9d2af4 100644
--- a/hw/rtl/VX_config.vh
+++ b/hw/rtl/VX_config.vh
@@ -233,6 +233,31 @@
 `define CSR_NW          12'hFC1
 `define CSR_NC          12'hFC2
 
+////////// Texture Unit CSRs /////////////
+`define CSR_TEX_BEGIN   12'hFD0
+// Unit 1
+`define CSR_TEX0_ADDR    `CSR_TEX_BEGIN
+`define CSR_TEX0_FORMAT  `CSR_TEX_BEGIN + 12'h1
+`define CSR_TEX0_WIDTH   `CSR_TEX_BEGIN + 12'h2
+`define CSR_TEX0_HEIGHT  `CSR_TEX_BEGIN + 12'h3
+`define CSR_TEX0_STRIDE  `CSR_TEX_BEGIN + 12'h4
+`define CSR_TEX0_WRAP_U  `CSR_TEX_BEGIN + 12'h5
+`define CSR_TEX0_WRAP_V  `CSR_TEX_BEGIN + 12'h6
+`define CSR_TEX0_MIN_FILTER  `CSR_TEX_BEGIN + 12'h7
+`define CSR_TEX0_MAX_FILTER  `CSR_TEX_BEGIN + 12'h8
+
+// Unit 2
+`define CSR_TEX1_ADDR    `CSR_TEX_BEGIN + 12'h9
+`define CSR_TEX1_FORMAT  `CSR_TEX_BEGIN + 12'hA
+`define CSR_TEX1_WIDTH   `CSR_TEX_BEGIN + 12'hB
+`define CSR_TEX1_HEIGHT  `CSR_TEX_BEGIN + 12'hC
+`define CSR_TEX1_STRIDE  `CSR_TEX_BEGIN + 12'hD
+`define CSR_TEX1_WRAP_U  `CSR_TEX_BEGIN + 12'hE
+`define CSR_TEX1_WRAP_V  `CSR_TEX_BEGIN + 12'hF
+`define CSR_TEX1_MIN_FILTER  `CSR_TEX_BEGIN + 12'h10
+`define CSR_TEX1_MAX_FILTER  `CSR_TEX_BEGIN + 12'h11
+
+`define CSR_TEX_END `CSR_TEX1_MAX_FILTER
 // Pipeline Queues ////////////////////////////////////////////////////////////
 
 // Size of LSU Request Queue
diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v
index 64e237e4..05fe8250 100644
--- a/hw/rtl/VX_csr_data.v
+++ b/hw/rtl/VX_csr_data.v
@@ -13,6 +13,7 @@ module VX_csr_data #(
 
     VX_cmt_to_csr_if                cmt_to_csr_if,
     VX_fpu_to_csr_if                fpu_to_csr_if,  
+    VX_tex_csr_if                   tex_csr_if,
 
     input wire                      read_enable,
     input wire[`CSR_ADDR_BITS-1:0]  read_addr,
@@ -53,7 +54,7 @@ module VX_csr_data #(
                                                           | fcsr[fpu_to_csr_if.write_wid][`FFG_BITS-1:0];
         end
 
-        if (write_enable) begin
+        if (write_enable && (write_addr > `CSR_TEX_END || write_addr < `CSR_TEX_BEGIN)) begin
             case (write_addr)
                 `CSR_FFLAGS:   fcsr[write_wid][`FFG_BITS-1:0] <= write_data[`FFG_BITS-1:0];
                 `CSR_FRM:      fcsr[write_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS] <= write_data[`FRM_BITS-1:0];
@@ -79,6 +80,11 @@ module VX_csr_data #(
         end
     end
 
+    //write tex csrs
+    assign tex_csr_if.write_addr = write_addr;
+    assign tex_csr_if.write_data = write_data;
+    assign tex_csr_if.write_enable = write_enable;
+
     always @(posedge clk) begin
        if (reset) begin
             csr_cycle   <= 0;
diff --git a/hw/rtl/VX_csr_unit.v b/hw/rtl/VX_csr_unit.v
index a282afe1..325dbdd1 100644
--- a/hw/rtl/VX_csr_unit.v
+++ b/hw/rtl/VX_csr_unit.v
@@ -12,7 +12,8 @@ module VX_csr_unit #(
 `endif
 
     VX_cmt_to_csr_if    cmt_to_csr_if, 
-    VX_fpu_to_csr_if    fpu_to_csr_if,  
+    VX_fpu_to_csr_if    fpu_to_csr_if, 
+    VX_tex_csr_if       tex_csr_if, 
     
     VX_csr_io_req_if    csr_io_req_if,    
     VX_csr_io_rsp_if    csr_io_rsp_if,
@@ -62,6 +63,7 @@ module VX_csr_unit #(
     `endif
         .cmt_to_csr_if  (cmt_to_csr_if),
         .fpu_to_csr_if  (fpu_to_csr_if), 
+        .tex_csr_if     (tex_csr_if),
         .read_enable    (csr_pipe_req_if.valid),
         .read_addr      (csr_pipe_req_if.addr),
         .read_wid       (csr_pipe_req_if.wid),      
diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh
index db1be050..139b2a05 100644
--- a/hw/rtl/VX_define.vh
+++ b/hw/rtl/VX_define.vh
@@ -385,6 +385,7 @@
 `define XDRAM_TAG_WIDTH         (`DDRAM_TAG_WIDTH+`CLOG2(2))
 
 ////////////////////////// Texture Unit Configurable Knobs //////////////////////////////
+`define NUM_TEX_UNITS 2 
 `define MADDRW      8           
 `define MAXWTW      8      
 `define MAXHTW      8      
diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.v
index 81e0b1cc..5ac78f35 100644
--- a/hw/rtl/VX_execute.v
+++ b/hw/rtl/VX_execute.v
@@ -45,6 +45,8 @@ module VX_execute #(
     output wire         ebreak
 );
     VX_fpu_to_csr_if     fpu_to_csr_if(); 
+    VX_tex_csr_if        tex_csr_if();
+
     wire[`NUM_WARPS-1:0] csr_pending;
     wire[`NUM_WARPS-1:0] fpu_pending;
     
@@ -82,6 +84,7 @@ module VX_execute #(
     `endif    
         .cmt_to_csr_if  (cmt_to_csr_if),    
         .fpu_to_csr_if  (fpu_to_csr_if), 
+        .tex_csr_if     (tex_csr_if),
         .csr_io_req_if  (csr_io_req_if),           
         .csr_io_rsp_if  (csr_io_rsp_if),
         .csr_req_if     (csr_req_if),   
@@ -129,7 +132,8 @@ module VX_execute #(
         .reset          (reset),    
         .gpu_req_if     (gpu_req_if),
         .warp_ctl_if    (warp_ctl_if),
-        .gpu_commit_if  (gpu_commit_if)
+        .gpu_commit_if  (gpu_commit_if),
+        .tex_csr_if     (tex_csr_if)
     );
 
     assign ebreak = alu_req_if.valid 
diff --git a/hw/rtl/VX_gpu_unit.v b/hw/rtl/VX_gpu_unit.v
index dadf50c7..9cad586d 100644
--- a/hw/rtl/VX_gpu_unit.v
+++ b/hw/rtl/VX_gpu_unit.v
@@ -10,6 +10,7 @@ module VX_gpu_unit #(
 
     // Inputs
     VX_gpu_req_if   gpu_req_if,
+    VX_tex_csr_if   tex_csr_if,
 
     // Outputs
     VX_warp_ctl_if  warp_ctl_if,
@@ -99,6 +100,7 @@ module VX_gpu_unit #(
         .reset          (reset),
 
         .tex_req_if     (tex_req_if),
+        .tex_csr_if     (tex_csr_if),
         .tex_rsp_if     (tex_rsp_if)
     );
 
diff --git a/hw/rtl/interfaces/VX_tex_csr_if.v b/hw/rtl/interfaces/VX_tex_csr_if.v
new file mode 100644
index 00000000..02422290
--- /dev/null
+++ b/hw/rtl/interfaces/VX_tex_csr_if.v
@@ -0,0 +1,20 @@
+`ifndef VX_TEX_CSR_IF
+`define VX_TEX_CSR_IF
+
+`include "VX_define.vh"
+
+interface VX_tex_csr_if ();
+
+    // wire                      read_enable;
+    // wire[`CSR_ADDR_BITS-1:0]  read_addr;
+    // wire[`NW_BITS-1:0]        read_wid;
+    // wire[31:0]               read_data;
+
+    wire                      write_enable; 
+    wire[`CSR_ADDR_BITS-1:0]  write_addr;
+    // wire[`NW_BITS-1:0]        write_wid;
+    wire[`CSR_WIDTH-1:0]      write_data;   
+
+endinterface
+
+`endif
\ No newline at end of file
diff --git a/hw/rtl/interfaces/VX_tex_req_if.v b/hw/rtl/interfaces/VX_tex_req_if.v
index 1d3fdf58..e8290587 100644
--- a/hw/rtl/interfaces/VX_tex_req_if.v
+++ b/hw/rtl/interfaces/VX_tex_req_if.v
@@ -8,6 +8,7 @@ interface VX_tex_req_if ();
     wire [`NUM_THREADS-1:0][31:0]           u;
     wire [`NUM_THREADS-1:0][31:0]           v;
     wire [`NUM_THREADS-1:0][31:0]           lod_t;
+    // wire [`NUM_THREADS-1:0][7:0]           t;
     // wire [`MADDRW-1:0]                   addr;    
     // wire [`MAXWTW-1:0]                   width;
     // wire [`MAXHTW-1:0]                   height;
diff --git a/hw/rtl/tex_unit/VX_tex_unit.v b/hw/rtl/tex_unit/VX_tex_unit.v
index d026a562..6961cb3c 100644
--- a/hw/rtl/tex_unit/VX_tex_unit.v
+++ b/hw/rtl/tex_unit/VX_tex_unit.v
@@ -8,6 +8,7 @@ module VX_tex_unit #(
     input wire  reset,
     // Inputs
     VX_tex_req_if   tex_req_if,
+    VX_tex_csr_if   tex_csr_if,
 
     // Outputs
     VX_tex_rsp_if   tex_rsp_if
@@ -43,8 +44,58 @@ module VX_tex_unit #(
     // output wire              cache_rsp_ready
 );
 
-    `UNUSED_VAR (clk)
+    // `UNUSED_VAR (clk)
     `UNUSED_VAR (reset)
+    `UNUSED_VAR (reset)
+
+    `UNUSED_VAR(tex_addr)
+    `UNUSED_VAR(tex_format)
+    `UNUSED_VAR(tex_width)
+    `UNUSED_VAR(tex_height)
+    `UNUSED_VAR(tex_stride)
+    `UNUSED_VAR(tex_wrap_u)
+    `UNUSED_VAR(tex_wrap_v)
+    `UNUSED_VAR(tex_min_filter)
+    `UNUSED_VAR(tex_max_filter)
+
+    reg [`CSR_WIDTH-1:0] tex_addr [`NUM_TEX_UNITS-1: 0]; 
+    reg [`CSR_WIDTH-1:0] tex_format [`NUM_TEX_UNITS-1: 0];
+    reg [`CSR_WIDTH-1:0] tex_width [`NUM_TEX_UNITS-1: 0];
+    reg [`CSR_WIDTH-1:0] tex_height [`NUM_TEX_UNITS-1: 0];
+    reg [`CSR_WIDTH-1:0] tex_stride [`NUM_TEX_UNITS-1: 0];
+    reg [`CSR_WIDTH-1:0] tex_wrap_u [`NUM_TEX_UNITS-1: 0];
+    reg [`CSR_WIDTH-1:0] tex_wrap_v [`NUM_TEX_UNITS-1: 0];
+    reg [`CSR_WIDTH-1:0] tex_min_filter [`NUM_TEX_UNITS-1: 0];
+    reg [`CSR_WIDTH-1:0] tex_max_filter [`NUM_TEX_UNITS-1: 0];
+
+    //tex csr programming, need to make make consistent with `NUM_TEX_UNITS
+    always @(posedge clk ) begin
+        if (tex_csr_if.write_enable) begin
+            case (tex_csr_if.write_addr)
+                `CSR_TEX0_ADDR : tex_addr[0] <= tex_csr_if.write_data;
+                `CSR_TEX0_FORMAT : tex_format[0] <= tex_csr_if.write_data;
+                `CSR_TEX0_WIDTH : tex_width[0] <= tex_csr_if.write_data;
+                `CSR_TEX0_HEIGHT : tex_height[0] <= tex_csr_if.write_data;
+                `CSR_TEX0_STRIDE : tex_stride[0] <= tex_csr_if.write_data;
+                `CSR_TEX0_WRAP_U : tex_wrap_u[0] <= tex_csr_if.write_data;
+                `CSR_TEX0_WRAP_V : tex_wrap_v[0] <= tex_csr_if.write_data;
+                `CSR_TEX0_MIN_FILTER : tex_min_filter[0] <= tex_csr_if.write_data;
+                `CSR_TEX0_MAX_FILTER : tex_max_filter[0] <= tex_csr_if.write_data;
+
+                `CSR_TEX1_ADDR : tex_addr[1] <= tex_csr_if.write_data;
+                `CSR_TEX1_FORMAT : tex_format[1] <= tex_csr_if.write_data;
+                `CSR_TEX1_WIDTH : tex_width[1] <= tex_csr_if.write_data;
+                `CSR_TEX1_HEIGHT : tex_height[1] <= tex_csr_if.write_data;
+                `CSR_TEX1_STRIDE : tex_stride[1] <= tex_csr_if.write_data;
+                `CSR_TEX1_WRAP_U : tex_wrap_u[1] <= tex_csr_if.write_data;
+                `CSR_TEX1_WRAP_V : tex_wrap_v[1] <= tex_csr_if.write_data;
+                `CSR_TEX1_MIN_FILTER : tex_min_filter[1] <= tex_csr_if.write_data;
+                `CSR_TEX1_MAX_FILTER : tex_max_filter[1] <= tex_csr_if.write_data;
+                default: 
+                    assert(tex_csr_if.write_addr > `CSR_TEX_END || tex_csr_if.write_addr < `CSR_TEX_BEGIN) else $error("%t: invalid CSR write address: %0h", $time, tex_csr_if.write_addr);
+            endcase
+        end
+    end
 
     for (genvar i = 0; i < `NUM_THREADS; i++) begin
         assign tex_rsp_if.data[i] = 32'hFAAF;
@@ -52,4 +103,21 @@ module VX_tex_unit #(
 
     assign tex_rsp_if.ready = 1'b1;
 
+    `ifdef DBG_PRINT_TEX_CSRS
+    always @(posedge clk) begin
+        if (tex_csr_if.write_addr <= `CSR_TEX_END || tex_csr_if.write_addr >= `CSR_TEX_BEGIN) begin
+            $display("%t: core%0d-tex_csr: csr_tex0_addr, csr_data=%0h", $time, CORE_ID, tex_addr[0]);
+            $display("%t: core%0d-tex_csr: csr_tex0_format, csr_data=%0h", $time, CORE_ID, tex_format[0]);
+            $display("%t: core%0d-tex_csr: csr_tex0_width, csr_data=%0h", $time, CORE_ID, tex_width[0]);
+            $display("%t: core%0d-tex_csr: csr_tex0_height, csr_data=%0h", $time, CORE_ID, tex_height[0]);
+            $display("%t: core%0d-tex_csr: csr_tex0_stride, csr_data=%0h", $time, CORE_ID, tex_stride[0]);
+            $display("%t: core%0d-tex_csr: csr_tex0_wrap_u, csr_data=%0h", $time, CORE_ID, tex_wrap_u[0]);
+            $display("%t: core%0d-tex_csr: csr_tex0_wrap_v, csr_data=%0h", $time, CORE_ID, tex_wrap_v[0]);
+            $display("%t: core%0d-tex_csr: csr_tex0_min_filter, csr_data=%0h", $time, CORE_ID, tex_min_filter[0]);
+            $display("%t: core%0d-tex_csr: csr_tex0_max_filter, csr_data=%0h", $time, CORE_ID, tex_max_filter[0]);
+        end
+    end
+    `endif 
+
+
 endmodule
\ No newline at end of file