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fixed DRAM response backpressure inside Cache

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This commit is contained in:
Blaise Tine
2020-11-10 05:24:57 -08:00
parent ed69be4027
commit 725322807e
19 changed files with 69 additions and 36 deletions
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2
hw/rtl/cache/VX_cache_miss_resrv.v vendored
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@@ -178,7 +178,7 @@ module VX_cache_miss_resrv #(
`ifdef DBG_PRINT_CACHE_MSRQ
always @(posedge clk) begin
if (schedule_st0 || enqueue_st3 || dequeue_st3) begin
if (update_ready_st0 || schedule_st0 || enqueue_st3 || dequeue_st3) begin
if (schedule_st0)
$display("%t: cache%0d:%0d msrq-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(dequeue_addr_st0, BANK_ID), debug_wid_st0, debug_pc_st0);
if (enqueue_st3) begin