fixed DRAM response backpressure inside Cache

2020-11-10 05:24:57 -08:00
parent ed69be4027
commit 725322807e
19 changed files with 69 additions and 36 deletions
--- a/hw/rtl/cache/VX_cache.v
+++ b/hw/rtl/cache/VX_cache.v
@@ -221,7 +221,7 @@ module VX_cache #(
    );

    assign dram_req_tag   = dram_req_addr;
-    assign dram_rsp_ready = (| per_bank_dram_rsp_ready);
+    assign dram_rsp_ready = (& per_bank_dram_rsp_ready);
    
    for (genvar i = 0; i < NUM_BANKS; i++) begin
        wire [NUM_REQUESTS-1:0]                             curr_bank_core_req_valid;