fixed DRAM response backpressure inside Cache

hw/rtl/cache/VX_bank.v

@@ -561,7 +561,7 @@ module VX_bank #(
     wire[WORD_SIZE-1:0]         req_byteen_st3;
 
     wire msrq_push_unqual = miss_st3 || force_miss_st3;
-    assign msrq_push_stall = (miss_st3 || force_miss_st3) && msrq_full;
+    assign msrq_push_stall = msrq_push_unqual && msrq_full;
 
     wire msrq_push = msrq_push_unqual
                   && !msrq_full 

hw/rtl/cache/VX_cache.v

@@ -221,7 +221,7 @@ module VX_cache #(
     );
 
     assign dram_req_tag   = dram_req_addr;
-    assign dram_rsp_ready = (| per_bank_dram_rsp_ready);
+    assign dram_rsp_ready = (& per_bank_dram_rsp_ready);
     
     for (genvar i = 0; i < NUM_BANKS; i++) begin
         wire [NUM_REQUESTS-1:0]                             curr_bank_core_req_valid;            

hw/rtl/cache/VX_cache_miss_resrv.v

@@ -178,7 +178,7 @@ module VX_cache_miss_resrv #(
 
 `ifdef DBG_PRINT_CACHE_MSRQ        
     always @(posedge clk) begin        
-        if (schedule_st0 || enqueue_st3 || dequeue_st3) begin
+        if (update_ready_st0 || schedule_st0 || enqueue_st3 || dequeue_st3) begin
             if (schedule_st0)
                 $display("%t: cache%0d:%0d msrq-schedule: addr%0d=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, schedule_ptr, `LINE_TO_BYTE_ADDR(dequeue_addr_st0, BANK_ID), debug_wid_st0, debug_pc_st0);      
             if (enqueue_st3) begin

hw/rtl/cache/VX_snp_forwarder.v

@@ -109,7 +109,7 @@ module VX_snp_forwarder #(
             .grant_onehot (sel_1hot)
         );
 
-        wire stall = fwdin_valid && ~fwdin_ready;
+        wire stall = ~fwdin_ready && fwdin_valid;
 
         VX_generic_register #(
             .N(1 + `LOG2UP(SNRQ_SIZE)),