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fixed opencl benchmarks

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This commit is contained in:
Blaise Tine
2020-03-09 09:55:16 -04:00
parent 857bb54f3f
commit 717a75ade8
64 changed files with 235418 additions and 1511751 deletions
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6
simX/Makefile
View File

@@ -2,8 +2,8 @@
# HARPtools by Chad D. Kersey, Summer 2011 #
################################################################################
CXXFLAGS ?= -std=c++11 -fPIC -O3 -Wall -Wextra -pedantic -g -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
# CXXFLAGS ?= -std=c++11 -fPIC -O0 -g -Wall -Wextra -pedantic # -g -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
CXXFLAGS ?= -std=c++11 -fPIC -O3 -Wall -Wextra -pedantic -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
#CXXFLAGS ?= -std=c++11 -fPIC -g -O0 -Wall -Wextra -pedantic -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
LIB_OBJS=simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp
@@ -28,7 +28,7 @@ all: simX
simX:
verilator $(COMP) -cc $(FILE) $(INCLUDE) $(EXE) $(LIB) $(CF) $(LIGHTW) $(DEB)
(cd obj_dir && make -j -f Vcache_simX.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
(cd obj_dir && make -j`nproc` -f Vcache_simX.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
clean:
rm -rf *~ \#* *.o *.a *.so include/*~ include/\#* simX.run obj_dir

8
simX/include/archdef.h
View File

@@ -16,7 +16,8 @@ namespace Harp {
public:
struct Undefined {};
ArchDef(const std::string &s) {
ArchDef(const std::string &s, bool cpu_mode = false)
: cpu_mode_(cpu_mode) {
std::istringstream iss(s.c_str());
wordSize = 4;
@@ -98,6 +99,10 @@ namespace Harp {
ThdNum getNWarps() const {
if (extent < EXT_WARPS) throw Undefined(); else return nWarps;
}
bool is_cpu_mode() const {
return cpu_mode_;
}
private:
enum Extent {
@@ -110,6 +115,7 @@ namespace Harp {
ThdNum nThds, nWarps;
RegNum nRegs, nPRegs;
char encChar;
bool cpu_mode_;
};
}

174
simX/instruction.cpp
View File

@@ -841,90 +841,100 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
case SYS_INST:
//std::cout << "SYS_INST\n";
temp = reg[rsrc[0]];
// if (immsrc == 0x20) // ThreadID
// {
// reg[rdest] = t;
// D(2, "CSR Reading tid " << hex << immsrc << dec << " and returning " << reg[rdest]);
// } else if (immsrc == 0x21) // WarpID
// {
// reg[rdest] = c.id;
// D(2, "CSR Reading wid " << hex << immsrc << dec << " and returning " << reg[rdest]);
// } else if (immsrc == 0x25)
// {
// reg[rdest] = c.core->num_instructions;
// } else if (immsrc == 0x26)
// {
// reg[rdest] = c.core->num_cycles;
// }
switch (func3)
{
case 1:
// printf("Case 1\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = temp;
break;
case 2:
// printf("Case 2\n");
if (rdest != 0)
{
// printf("Reading from CSR: %d = %d\n", (immsrc & 0x00000FFF), c.csr[immsrc & 0x00000FFF]);
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
// printf("Writing to CSR --> %d = %d\n", immsrc, (temp | c.csr[immsrc & 0x00000FFF]));
c.csr[immsrc & 0x00000FFF] = temp | c.csr[immsrc & 0x00000FFF];
break;
case 3:
// printf("Case 3\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = temp & (~c.csr[immsrc & 0x00000FFF]);
break;
case 5:
// printf("Case 5\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = rsrc[0];
break;
case 6:
// printf("Case 6\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = rsrc[0] | c.csr[immsrc & 0x00000FFF];
break;
case 7:
// printf("Case 7\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = rsrc[0] & (~c.csr[immsrc & 0x00000FFF]);
break;
case 0:
if (immsrc < 2)
if (!c.core->a.is_cpu_mode()) {
//
// GPGPU CSR extension
//
if (immsrc == 0x20) // ThreadID
{
//std::cout << "INTERRUPT ECALL/EBREAK\n";
nextActiveThreads = 0;
c.spawned = false;
// c.interrupt(0);
reg[rdest] = t;
D(2, "CSR Reading tid " << hex << immsrc << dec << " and returning " << reg[rdest]);
}
else if (immsrc == 0x21) // WarpID
{
reg[rdest] = c.id;
D(2, "CSR Reading wid " << hex << immsrc << dec << " and returning " << reg[rdest]);
}
else if (immsrc == 0x25)
{
reg[rdest] = c.core->num_instructions;
}
else if (immsrc == 0x26)
{
reg[rdest] = c.core->num_cycles;
}
} else {
switch (func3)
{
case 1:
// printf("Case 1\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = temp;
break;
case 2:
// printf("Case 2\n");
if (rdest != 0)
{
// printf("Reading from CSR: %d = %d\n", (immsrc & 0x00000FFF), c.csr[immsrc & 0x00000FFF]);
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
// printf("Writing to CSR --> %d = %d\n", immsrc, (temp | c.csr[immsrc & 0x00000FFF]));
c.csr[immsrc & 0x00000FFF] = temp | c.csr[immsrc & 0x00000FFF];
break;
case 3:
// printf("Case 3\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = temp & (~c.csr[immsrc & 0x00000FFF]);
break;
case 5:
// printf("Case 5\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = rsrc[0];
break;
case 6:
// printf("Case 6\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = rsrc[0] | c.csr[immsrc & 0x00000FFF];
break;
case 7:
// printf("Case 7\n");
if (rdest != 0)
{
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
c.csr[immsrc & 0x00000FFF] = rsrc[0] & (~c.csr[immsrc & 0x00000FFF]);
break;
case 0:
if (immsrc < 2)
{
//std::cout << "INTERRUPT ECALL/EBREAK\n";
nextActiveThreads = 0;
c.spawned = false;
// c.interrupt(0);
}
break;
default:
break;
}
break;
default:
break;
}
break;
case TRAP:

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simX/obj_dir/Vcache_simX
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80
simX/obj_dir/Vcache_simX__verFiles.dat
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@@ -1,43 +1,43 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wall -Wextra -pedantic -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1"
S 26 1407374883617647 1583036691 972658000 1583036691 972658000 "../rtl/./VX_define_synth.v"
S 283 1407374883617640 1583036691 969666100 1583036691 969666100 "../rtl/VX_countones.v"
S 7257 1407374883617646 1583036691 972658000 1583036691 972658000 "../rtl/VX_define.v"
S 8325 1407374883617648 1583036691 973655300 1583036691 973655300 "../rtl/VX_dmem_controller.v"
S 517 1407374883617652 1583036691 975649300 1583036691 975649300 "../rtl/VX_generic_priority_encoder.v"
S 683 1407374883617664 1583036691 981634100 1583036691 981634100 "../rtl/VX_priority_encoder_w_mask.v"
S 8590 1407374883617675 1583036691 985623400 1583036691 985623400 "../rtl/cache/VX_Cache_Bank.v"
S 748 1407374883617676 1583036691 986620700 1583036691 986620700 "../rtl/cache/VX_cache_bank_valid.v"
S 7349 1407374883617677 1583036691 986620700 1583036691 986620700 "../rtl/cache/VX_cache_data.v"
S 6476 1407374883617678 1583036691 987617400 1583036691 987617400 "../rtl/cache/VX_cache_data_per_index.v"
S 14645 1407374883617679 1583036691 987617400 1583036691 987617400 "../rtl/cache/VX_d_cache.v"
S 393 1407374883617692 1583036691 993601900 1583036691 993601900 "../rtl/interfaces/VX_dcache_request_inter.v"
S 215 1407374883617693 1583036691 994599200 1583036691 994599200 "../rtl/interfaces/VX_dcache_response_inter.v"
S 870 1407374883617694 1583036691 994599200 1583036691 994599200 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
S 354 1407374883617709 1583036691 999585900 1583036691 999585900 "../rtl/interfaces/VX_icache_request_inter.v"
S 212 1407374883617710 1583036691 999585900 1583036691 999585900 "../rtl/interfaces/VX_icache_response_inter.v"
S 7257 1407374883617646 1583036691 972658000 1583036691 972658000 "../rtl/shared_memory/../VX_define.v"
S 676 1407374883617754 1583036692 20529900 1583036692 20529900 "../rtl/shared_memory/VX_bank_valids.v"
S 3038 1407374883617755 1583036692 21526400 1583036692 21526400 "../rtl/shared_memory/VX_priority_encoder_sm.v"
S 4962 1407374883617756 1583036692 22524600 1583036692 22524600 "../rtl/shared_memory/VX_shared_memory.v"
S 3207 1407374883617757 1583036692 22524600 1583036692 22524600 "../rtl/shared_memory/VX_shared_memory_block.v"
S 26 1407374883678355 1576858113 365285900 1576858113 365285900 "../rtl/./VX_define_synth.v"
S 283 1407374883678346 1576858113 363291200 1576858113 363291200 "../rtl/VX_countones.v"
S 7257 5629499534267235 1583028100 893817800 1583028100 893817800 "../rtl/VX_define.v"
S 8325 1407374883678357 1576858113 366283200 1576858113 366283200 "../rtl/VX_dmem_controller.v"
S 517 1407374883678365 1576858113 368277800 1576858113 368277800 "../rtl/VX_generic_priority_encoder.v"
S 683 1407374883678386 1576858113 374262300 1576858113 374262300 "../rtl/VX_priority_encoder_w_mask.v"
S 8590 1407374883678402 1576858113 378252100 1576858113 378252100 "../rtl/cache/VX_Cache_Bank.v"
S 748 1407374883678406 1576858113 379248400 1576858113 379248400 "../rtl/cache/VX_cache_bank_valid.v"
S 7349 1407374883678408 1576858113 380246000 1576858113 380246000 "../rtl/cache/VX_cache_data.v"
S 6476 1407374883678409 1576858113 380246000 1576858113 380246000 "../rtl/cache/VX_cache_data_per_index.v"
S 14645 1407374883678410 1576858113 381243100 1576858113 381243100 "../rtl/cache/VX_d_cache.v"
S 393 1407374883678432 1576858113 386229700 1576858113 386229700 "../rtl/interfaces/VX_dcache_request_inter.v"
S 215 1407374883678434 1576858113 387227400 1576858113 387227400 "../rtl/interfaces/VX_dcache_response_inter.v"
S 870 1407374883678435 1576858113 387227400 1576858113 387227400 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
S 354 1407374883678447 1576858113 392213800 1576858113 392213800 "../rtl/interfaces/VX_icache_request_inter.v"
S 212 1407374883678448 1576858113 392213800 1576858113 392213800 "../rtl/interfaces/VX_icache_response_inter.v"
S 7257 5629499534267235 1583028100 893817800 1583028100 893817800 "../rtl/shared_memory/../VX_define.v"
S 676 1407374883678497 1576858113 417147000 1576858113 417147000 "../rtl/shared_memory/VX_bank_valids.v"
S 3038 1407374883678498 1576858113 418144200 1576858113 418144200 "../rtl/shared_memory/VX_priority_encoder_sm.v"
S 4962 1407374883678499 1576858113 418144200 1576858113 418144200 "../rtl/shared_memory/VX_shared_memory.v"
S 3207 1407374883678500 1576858113 419141900 1576858113 419141900 "../rtl/shared_memory/VX_shared_memory_block.v"
S 5279832 1125899907857040 1579658333 790142700 1519110675 0 "/usr/bin/verilator_bin"
S 3144 1407374883617983 1583036693 278327800 1583036693 278327800 "cache_simX.v"
T 390173 4222124650721525 1583038884 772480200 1583038884 772480200 "obj_dir/Vcache_simX.cpp"
T 28278 5066549580853492 1583038884 765499600 1583038884 765499600 "obj_dir/Vcache_simX.h"
T 2365 18858823439675736 1583038884 803378700 1583038884 803378700 "obj_dir/Vcache_simX.mk"
T 643931 2533274790457603 1583038884 802128000 1583038884 802128000 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp"
T 23659 2533274790457602 1583038884 788131800 1583038884 788131800 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h"
T 578414 2533274790457601 1583038884 787134700 1583038884 787134700 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.cpp"
T 23321 4222124650721534 1583038884 776161100 1583038884 776161100 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.h"
T 1024 2251799813746939 1583038884 775163700 1583038884 775163700 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
T 1561 5348024557564153 1583038884 774165800 1583038884 774165800 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
T 999 2533274790457592 1583038884 773299100 1583038884 773299100 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
T 1557 2814749767168246 1583038884 773299100 1583038884 773299100 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
T 6004 14073748835594442 1583038884 720643500 1583038884 720643500 "obj_dir/Vcache_simX__Syms.cpp"
T 2455 3096224743878468 1583038884 719619200 1583038884 719619200 "obj_dir/Vcache_simX__Syms.h"
T 1114242 5066549580853489 1583038884 763504200 1583038884 763504200 "obj_dir/Vcache_simX__Trace.cpp"
T 1433229 3377699720589552 1583038884 745891000 1583038884 745891000 "obj_dir/Vcache_simX__Trace__Slow.cpp"
T 1439 1688849860325816 1583038884 804364500 1583038884 804364500 "obj_dir/Vcache_simX__ver.d"
T 0 0 1583038884 836313300 1583038884 836313300 "obj_dir/Vcache_simX__verFiles.dat"
T 1392 2251799813746948 1583038884 802128000 1583038884 802128000 "obj_dir/Vcache_simX_classes.mk"
S 3144 1407374883678789 1576858114 576047000 1576858114 576047000 "cache_simX.v"
T 390173 22236523160217637 1583612769 755410900 1583612769 755410900 "obj_dir/Vcache_simX.cpp"
T 28278 15481123719153127 1583612769 748398500 1583612769 748398500 "obj_dir/Vcache_simX.h"
T 2365 10133099161813405 1583612769 784337500 1583612769 784337500 "obj_dir/Vcache_simX.mk"
T 643931 3940649674155161 1583612769 783340900 1583612769 783340900 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp"
T 23659 5348024557708078 1583612769 771372900 1583612769 771372900 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h"
T 578414 15481123719285399 1583612769 770399200 1583612769 770399200 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.cpp"
T 23321 11258999068615501 1583612769 760411300 1583612769 760411300 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.h"
T 1024 8725724278219266 1583612769 757374600 1583612769 757374600 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
T 1561 50102545854682183 1583612769 757374600 1583612769 757374600 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
T 999 10414574138447661 1583612769 756377900 1583612769 756377900 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
T 1557 6755399441176779 1583612769 756377900 1583612769 756377900 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
T 6004 11821949021903061 1583612769 706686400 1583612769 706686400 "obj_dir/Vcache_simX__Syms.cpp"
T 2455 32088147345022597 1583612769 705722700 1583612769 705722700 "obj_dir/Vcache_simX__Syms.h"
T 1114242 10414574138355386 1583612769 747434700 1583612769 747434700 "obj_dir/Vcache_simX__Trace.cpp"
T 1433229 12103423998619303 1583612769 729412200 1583612769 729412200 "obj_dir/Vcache_simX__Trace__Slow.cpp"
T 1439 6755399441290555 1583612769 784337500 1583612769 784337500 "obj_dir/Vcache_simX__ver.d"
T 0 0 1583612769 844870300 1583612769 844870300 "obj_dir/Vcache_simX__verFiles.dat"
T 1392 4785074604292692 1583612769 784337500 1583612769 784337500 "obj_dir/Vcache_simX_classes.mk"

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8
simX/simX.cpp
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@@ -55,8 +55,10 @@ HarpToolMode findMode(int argc, char** argv) {
}
int emu_main(int argc, char **argv) {
string archString("rv32i"), imgFileName("a.dsfsdout.bin");
string archString("rv32i");
string imgFileName("a.dsfsdout.bin");
bool showHelp, showStats, basicMachine, batch;
bool cpu_mode(false);
/* Read the command line arguments. */
CommandLineArgFlag fh("-h", "--help", "", showHelp);
@@ -65,15 +67,17 @@ int emu_main(int argc, char **argv) {
CommandLineArgFlag fs("-s", "--stats", "", showStats);
CommandLineArgFlag fb("-b", "--basic", "", basicMachine);
CommandLineArgFlag fi("-i", "--batch", "", batch);
CommandLineArgFlag fx("-x", "--cpu", "", cpu_mode);
CommandLineArg::readArgs(argc, argv);
if (showHelp) {
cout << Help::emuHelp;
return 0;
}
/* Instantiate a Core, RAM, and console output. */
ArchDef arch(archString);
ArchDef arch(archString, cpu_mode);
Decoder *dec;

145
simX/test_riscv.sh
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@@ -1,7 +1,142 @@
make
cd obj_dir
echo start > results.txt
# echo ../kernel/vortex_test.hex
make
printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
#cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../runtime/mains/simple/vx_simple_main.hex -s -b 1> emulator.debug
cd obj_dir && ./Vcache_simX -E -a rv32i --core /home/priya/Desktop/new_vortex/Vortex/rvvector/benchmark_temp/vx_vec_benchmark.hex -s -b 1> emulator.debug
echo ./riscv_tests/rv32ui-p-add.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-add.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-addi.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-addi.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-and.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-and.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-andi.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-andi.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-auipc.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-auipc.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-beq.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-beq.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bge.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bge.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bgeu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bgeu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-blt.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-blt.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bltu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bltu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bne.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-bne.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-jal.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-jal.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-jalr.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-jalr.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lb.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lb.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lbu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lbu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lh.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lh.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lhu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lhu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lui.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lui.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lw.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-lw.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-or.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-or.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-ori.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-ori.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sb.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sb.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sh.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sh.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-simple.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-simple.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sll.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sll.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-slli.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slli.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-slt.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slt.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-slti.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-slti.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sltiu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sltiu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sltu.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sltu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sra.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sra.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-srai.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srai.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-srl.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srl.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-srli.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-srli.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sub.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sub.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sw.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-sw.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-xor.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-xor.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-xori.hex >> results.txt
./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32ui-p-xori.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-div.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-div.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-divu.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-divu.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mul.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mul.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mulh.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulh.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mulhsu.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulhsu.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mulhu.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-mulhu.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-rem.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-rem.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-remu.hex >> results.txt
# ./Vcache_simX -E --cpu -a rv32i --core ../riscv_tests/rv32um-p-remu.hex -s -b >> results.txt

17
simX/test_runtime.sh Executable file
View File

@@ -0,0 +1,17 @@
make
make -C ../runtime/mains/dev
make -C ../runtime/mains/hello
make -C ../runtime/mains/nativevecadd
make -C ../runtime/mains/simple
make -C ../runtime/mains/vecadd
cd obj_dir
echo start > results.txt
printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
#./Vcache_simX -E -a rv32i --core ../../runtime/mains/dev/vx_dev_main.hex -s -b 1> emulator.debug
#./Vcache_simX -E -a rv32i --core ../../runtime/mains/hello/hello.hex -s -b 1> emulator.debug
./Vcache_simX -E -a rv32i --core ../../runtime/mains/nativevecadd/vx_pocl_main.hex -s -b 1> emulator.debug
./Vcache_simX -E -a rv32i --core ../../runtime/mains/simple/vx_simple_main.hex -s -b 1> emulator.debug
./Vcache_simX -E -a rv32i --core ../../runtime/mains/vecadd/vx_pocl_main.hex -s -b 1> emulator.debug

145
simX/test_rv32ui.sh
View File

@@ -1,145 +0,0 @@
make
cd obj_dir
echo start > results.txt
echo ./riscv_tests/rv32ui-p-add.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-add.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-addi.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-addi.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-and.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-and.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-andi.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-andi.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-auipc.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-auipc.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-beq.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-beq.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bge.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-bge.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bgeu.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-bgeu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-blt.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-blt.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bltu.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-bltu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-bne.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-bne.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-jal.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-jal.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-jalr.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-jalr.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lb.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lb.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lbu.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lbu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lh.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lh.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lhu.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lhu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lui.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lui.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-lw.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-lw.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-or.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-or.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-ori.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-ori.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sb.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sb.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sh.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sh.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-simple.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-simple.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sll.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sll.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-slli.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-slli.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-slt.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-slt.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-slti.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-slti.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sltiu.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sltiu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sltu.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sltu.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sra.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sra.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-srai.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-srai.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-srl.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-srl.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-srli.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-srli.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sub.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sub.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-sw.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-sw.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-xor.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-xor.hex -s -b >> results.txt
echo ./riscv_tests/rv32ui-p-xori.hex >> results.txt
./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32ui-p-xori.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-div.hex >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-div.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-divu.hex >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-divu.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mul.hex >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-mul.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mulh.hex >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-mulh.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mulhsu.hex >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-mulhsu.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-mulhu.hex >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-mulhu.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-rem.hex >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-rem.hex -s -b >> results.txt
# echo ./riscv_tests/rv32um-p-remu.hex >> results.txt
# ./Vcache_simX -E -a rv32i --core ../riscv_tests/rv32um-p-remu.hex -s -b >> results.txt