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Modelsim Working + Simulating + dumping - Some bugs

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This commit is contained in:
felsabbagh3
2019-10-27 03:36:02 -04:00
parent 372c81d90c
commit 715982cca7
24 changed files with 374 additions and 142 deletions
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40
rtl/modelsim/Makefile
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@@ -1,18 +1,4 @@
###############################################################################
#
# ICARUS VERILOG & GTKWAVE MAKEFILE
# MADE BY WILLIAM GIBB FOR HACDC
# williamgibb@gmail.com
#
# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE
# "make check" - compiles your verilog design - good for checking code
# "make simulate" - compiles your design+TB & simulates your design
# "make display" - compiles, simulates and displays waveforms
#
###############################################################################
#
# CHANGE THESE THREE LINES FOR YOUR DESIGN
#
ALL:sim
@@ -86,13 +72,14 @@ SRC = \
../shared_memory/VX_bank_valids.v \
../shared_memory/VX_priority_encoder_sm.v \
../shared_memory/VX_shared_memory.v \
../shared_memory/VX_shared_memory_block.v
../shared_memory/VX_shared_memory_block.v \
vortex_dpi.cpp
CMD= \
-do "vcd file vortex.vcd; \
vcd add -r vortex_tb; \
run; \
vcd add -r /vortex/*; \
run -all; \
quit -f"
@@ -103,26 +90,11 @@ LIB = vortex_lib
# LOG=-logfile vortex_tb.log
LOG=
# ../shared_memory/VX_set_bit.v \
# ../cache/bank.v \
# ../cache/VX_d_cache_tb.v \
# ../cache/VX_d_cache_encapsulate.v \
# ../VX_rename.v \
# ../cache/VX_Cache_Block_DM.v \
# ../VX_one_counter.v \
###############################################################################
# BE CAREFUL WHEN CHANGING ITEMS BELOW THIS LINE
###############################################################################
#TOOLS
#TOOL OUTPUT
###############################################################################
#MAKE DIRECTIVES
# setup: source cshrc.modelsim
# vlib
comp:
vlog $(OPT) -work $(LIB) $(SRC)
vlog -O0 $(OPT) -work $(LIB) $(SRC)
sim: comp

145
rtl/modelsim/vortex_dpi.cpp Normal file
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@@ -0,0 +1,145 @@
// #include <iostream>
// #include "VX_define.h"
#include <../simulate/ram.h>
#include <stdio.h>
#include "svdpi.h"
#include "../simulate/VX_define.h"
extern "C" {
void load_file(char * filename);
void ibus_driver(int pc_addr, int * instruction);
void dbus_driver(int o_m_read_addr, int o_m_evict_addr, bool o_m_valid, int * o_m_writedata, bool o_m_read_or_write, int * i_m_readdata, bool * i_m_ready);
void io_handler(bool io_valid, int io_data);
}
RAM ram;
unsigned getIndex(int r, int c, int numCols)
{
return (r * numCols) + c;
}
void load_file(char * filename)
{
printf("\n\n\n\n**********************\n");
// printf("Inside load_file\n");
loadHexImpl(filename, &ram);
// printf("Filename: %s\n", filename);
}
void ibus_driver(int pc_addr, int * instruction)
{
// printf("Inside ibus_driver\n");
uint32_t curr_inst = 0;
curr_inst = 0xdeadbeef;
uint32_t u_pc_addr = (uint32_t) (pc_addr);
ram.getWord(u_pc_addr, &curr_inst);
// printf("PC_addr: %x, instruction: %x\n", pc_addr, instruction);
(*instruction) = curr_inst;
}
bool refill;
unsigned refill_addr;
void dbus_driver(int o_m_read_addr, int o_m_evict_addr, bool o_m_valid, int * o_m_writedata, bool o_m_read_or_write, int * i_m_readdata, bool * i_m_ready)
{
// printf("Inside dbus_driver\n");
(*i_m_ready )= 0;
for (int i = 0; i < CACHE_NUM_BANKS; i++)
{
for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
{
i_m_readdata[getIndex(i,j, CACHE_WORDS_PER_BLOCK)] = 0;
}
}
if (refill)
{
refill = false;
*i_m_ready = 1;
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
{
unsigned new_addr = refill_addr + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bank_num = addr_without_byte & 0x7;
unsigned addr_wihtout_bank = addr_without_byte >> 3;
unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned value;
ram.getWord(new_addr, &value);
// printf("-------- (%x) i_m_readdata[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value);
i_m_readdata[getIndex(bank_num,offset_num, CACHE_NUM_BANKS)] = value;
}
}
else
{
if (o_m_valid)
{
// printf("Valid o_m_valid\n");
if (o_m_read_or_write)
{
// printf("Valid write\n");
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
{
unsigned new_addr = (o_m_evict_addr) + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bank_num = addr_without_byte & 0x7;
unsigned addr_wihtout_bank = addr_without_byte >> 3;
unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, CACHE_NUM_BANKS)];
ram.writeWord( new_addr, &new_value);
// printf("+++++++ (%x) writeback[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, new_value);
// printf("+++++++ (%x) i_m_readdata[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value);
}
}
// Respond next cycle
refill = true;
refill_addr = o_m_read_addr;
}
}
}
void io_handler(bool io_valid, int io_data)
{
// printf("Inside io_handler\n");
if (io_valid)
{
uint32_t data_write = (uint32_t) (io_data);
char c = (char) data_write;
printf("%c", c);
printf("YOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYOYO\n");
fflush(stdout);
}
}

88
rtl/modelsim/vortex_tb.v
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@@ -1,8 +1,29 @@
// `include "../VX_define.v"
// `include "../Vortex.v"
`include "../VX_define.v"
`define NUMBER_BANKS 8
`define NUM_WORDS_PER_BLOCK 4
`timescale 1ns/1ps
import "DPI-C" load_file = function void load_file(input string filename);
import "DPI-C" ibus_driver = function void ibus_driver(input int pc_addr,
output int instruction);
import "DPI-C" dbus_driver = function void dbus_driver( input int o_m_read_addr,
input int o_m_evict_addr,
input reg o_m_valid,
input reg [31:0] o_m_writedata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
input reg o_m_read_or_write,
// Rsp
output reg [31:0] i_m_readdata[`NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0],
output reg i_m_ready);
import "DPI-C" io_handler = function void io_handler(input reg io_valid, input int io_data);
module vortex_tb (
);
@@ -26,21 +47,21 @@ module vortex_tb (
reg i_m_ready;
reg out_ebreak;
integer temp;
initial begin
// $dumpfile("vortex2.vcd");
$dumpvars(0, vortex);
for (temp = 0; temp < 10; temp=temp+1)
begin
if (temp == 0) begin
icache_response_instruction = 32'h00000513;
$display("Cycle 1");
end if (temp == 1) begin
$display("Cycle 2",);
icache_response_instruction = 32'h0005006b;
end
end
reg[31:0] hi;
integer temp;
integer num_cycles;
initial begin
// $fdumpfile("vortex1.vcd");
load_file("../../kernel/vortex_test.hex");
$dumpvars(0, vortex_tb);
reset = 1;
clk = 0;
#5 reset = 1;
clk = 1;
num_cycles = 0;
end
Vortex vortex(
@@ -61,6 +82,37 @@ module vortex_tb (
);
always @(clk) #5 clk <= ~clk;
always @(clk, posedge reset) begin
// $display("FROM ALWAYS");
// $display("num_cycles: %d",num_cycles);
num_cycles = num_cycles + 1;
if (num_cycles == 1000) begin
// $dumpall;
// $dumpflush;
// $finish;
end
// if (num_cycles == 1000) $stop;
if (reset) begin
reset = 0;
clk = 0;
end
if (clk == 0) begin
ibus_driver(icache_request_pc_address, icache_response_instruction);
dbus_driver(o_m_read_addr, o_m_evict_addr, o_m_valid, o_m_writedata, o_m_read_or_write, i_m_readdata, i_m_ready);
io_handler(io_valid, io_data);
end
// $display("clk: %d, out_ebreak: %d",clk, out_ebreak);
#5 clk <= ~clk;
if (out_ebreak) $finish;
end
endmodule
endmodule