Modelsim Working + Simulating + dumping - Some bugs

2019-10-27 03:36:02 -04:00
parent 372c81d90c
commit 715982cca7
24 changed files with 374 additions and 142 deletions
--- a/rtl/cache/VX_Cache_Bank.v
+++ b/rtl/cache/VX_Cache_Bank.v
@@ -15,6 +15,7 @@ module VX_Cache_Bank
            )
          (
            clk,
+            rst,
            state,
            read_or_write, // Read = 0 | Write = 1
           i_p_mem_read,
@@ -49,6 +50,7 @@ module VX_Cache_Bank
    localparam RECIV_MEM_RSP = 2;

    // Inputs
+    input wire rst;
    input wire clk;
    input wire [3:0] state;
 //input wire write_from_mem;
@@ -175,6 +177,7 @@ module VX_Cache_Bank
          .CACHE_BANKS(CACHE_BANKS),
          .NUM_WORDS_PER_BLOCK(NUM_WORDS_PER_BLOCK)) data_structures(
        .clk       (clk),
+        .rst       (rst),
        // Inputs
        .addr      (actual_index),
        .we        (we),