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Modelsim Working + Simulating + dumping - Some bugs

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This commit is contained in:
felsabbagh3
2019-10-27 03:36:02 -04:00
parent 372c81d90c
commit 715982cca7
24 changed files with 374 additions and 142 deletions
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3
rtl/cache/VX_Cache_Bank.v vendored
View File

@@ -15,6 +15,7 @@ module VX_Cache_Bank
)
(
clk,
rst,
state,
read_or_write, // Read = 0 | Write = 1
i_p_mem_read,
@@ -49,6 +50,7 @@ module VX_Cache_Bank
localparam RECIV_MEM_RSP = 2;
// Inputs
input wire rst;
input wire clk;
input wire [3:0] state;
//input wire write_from_mem;
@@ -175,6 +177,7 @@ module VX_Cache_Bank
.CACHE_BANKS(CACHE_BANKS),
.NUM_WORDS_PER_BLOCK(NUM_WORDS_PER_BLOCK)) data_structures(
.clk (clk),
.rst (rst),
// Inputs
.addr (actual_index),
.we (we),

41
rtl/cache/VX_cache_data.v vendored
View File

@@ -11,7 +11,7 @@ module VX_cache_data
parameter NUM_WORDS_PER_BLOCK = 4
)
(
input wire clk, // Clock
input wire clk, rst, // Clock
// Addr
input wire[`CACHE_IND_SIZE_RNG] addr,
@@ -56,29 +56,30 @@ module VX_cache_data
assign valid_use = valid[addr];
assign dirty_use = dirty[addr];
always @(posedge clk) begin : dirty_update
if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
end
integer f;
always @(posedge clk) begin : data_update
for (f = 0; f < NUM_WORDS_PER_BLOCK; f = f + 1) begin
if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ];
if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ];
if (we[f][2]) data[addr][f][2] <= data_write[f][23:16];
if (we[f][3]) data[addr][f][3] <= data_write[f][31:24];
integer ini_ind;
always @(posedge clk, posedge rst) begin : update_all
if (rst) begin
for (ini_ind = 0; ini_ind < NUMBER_INDEXES; ini_ind=ini_ind+1) begin
data[ini_ind] = 0;
tag[ini_ind] = 0;
valid[ini_ind] = 0;
dirty[ini_ind] = 0;
end
end else begin
if (update_dirty) dirty[addr] <= dirt_new; // WRite Port
if (evict) tag[addr] <= tag_write;
if (evict) valid[addr] <= 1;
for (f = 0; f < NUM_WORDS_PER_BLOCK; f = f + 1) begin
if (we[f][0]) data[addr][f][0] <= data_write[f][7 :0 ];
if (we[f][1]) data[addr][f][1] <= data_write[f][15:8 ];
if (we[f][2]) data[addr][f][2] <= data_write[f][23:16];
if (we[f][3]) data[addr][f][3] <= data_write[f][31:24];
end
end
end
always @(posedge clk) begin : tag_update
if (evict) tag[addr] <= tag_write;
end
always @(posedge clk) begin : valid_update
if (evict) valid[addr] <= 1;
end
`else

36
rtl/cache/VX_d_cache.v vendored
View File

@@ -206,19 +206,36 @@ module VX_d_cache
// Handle if there is more than one miss
assign new_stored_valid = use_valid & (~threads_serviced_Qual);
///////////////////////////////////////////////////////////////////////
genvar cur_t;
always @(posedge clk) begin
state <= new_state;
integer init_b;
always @(posedge clk, posedge rst) begin
if (rst) begin
final_data_read <= 0;
new_final_data_read = 0;
state <= 0;
stored_valid <= 0;
// eviction_addr_per_bank <= 0;
miss_addr <= 0;
evict_addr <= 0;
// threads_serviced_Qual = 0;
// for (init_b = 0; init_b < NUMBER_BANKS; init_b=init_b+1)
// begin
// debug_hit_per_bank_mask[init_b] <= 0;
// end
end else begin
state <= new_state;
stored_valid <= new_stored_valid;
stored_valid <= new_stored_valid;
if (miss_found) begin
miss_addr <= i_p_addr[send_index_to_bank[miss_bank_index]];
evict_addr <= eviction_addr_per_bank[miss_bank_index];
if (miss_found) begin
miss_addr <= i_p_addr[send_index_to_bank[miss_bank_index]];
evict_addr <= eviction_addr_per_bank[miss_bank_index];
end
final_data_read <= new_final_data_read_Qual;
end
final_data_read <= new_final_data_read_Qual;
end
@@ -250,6 +267,7 @@ module VX_d_cache
.CACHE_BANKS(CACHE_BANKS)) bank_structure
(
.clk (clk),
.rst (rst),
.state (state),
.valid_in (use_valid_in),
.actual_index (cache_index),