Modelsim Working + Simulating + dumping - Some bugs

2019-10-27 03:36:02 -04:00
parent 372c81d90c
commit 715982cca7
24 changed files with 374 additions and 142 deletions
--- a/rtl/VX_dmem_controller.v
+++ b/rtl/VX_dmem_controller.v
@@ -1,5 +1,5 @@

-// `include "VX_define.v"
+`include "VX_define.v"

 module VX_dmem_controller (
 	input wire               clk,
@@ -39,6 +39,7 @@ module VX_dmem_controller (

 	VX_shared_memory #(.NB(7), .BITS_PER_BANK(3)) shared_memory (
 		.clk       (clk),
+		.reset     (reset),
 		.in_valid  (sm_driver_in_valid),
 		.in_address(cache_driver_in_address),
 		.in_data   (cache_driver_in_data),