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Added a pipeline stage + fixed SM param errors

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This commit is contained in:
felsabbagh3
2019-11-13 12:25:28 -05:00
parent 7f7d17d176
commit 70651f0340
15 changed files with 26390 additions and 24621 deletions
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4
rtl/VX_define.v
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@@ -258,8 +258,8 @@
`define SHARED_MEMORY_HEIGHT ((`SHARED_MEMORY_SIZE) / (`SHARED_MEMORY_BANKS * `SHARED_MEMORY_BYTES_PER_READ)) `define SHARED_MEMORY_HEIGHT ((`SHARED_MEMORY_SIZE) / (`SHARED_MEMORY_BANKS * `SHARED_MEMORY_BYTES_PER_READ))
`define SHARED_MEMORY_BANK_OFFSET_ST (2) `define SHARED_MEMORY_BANK_OFFSET_ST (2)
`define SHARED_MEMORY_BANK_OFFSET_ED (2+$clog2(`DCACHE_BANKS)-1) `define SHARED_MEMORY_BANK_OFFSET_ED (2+$clog2(`SHARED_MEMORY_BANKS)-1)
`define SHARED_MEMORY_BLOCK_OFFSET_ST (`SHARED_MEMORY_BANK_OFFSET_ED + 1) `define SHARED_MEMORY_BLOCK_OFFSET_ST (`SHARED_MEMORY_BANK_OFFSET_ED + 1)
`define SHARED_MEMORY_BLOCK_OFFSET_ED (`SHARED_MEMORY_BLOCK_OFFSET_ST +$clog2(`SHARED_MEMORY_LOG_WORDS_PER_READ)-1) `define SHARED_MEMORY_BLOCK_OFFSET_ED (`SHARED_MEMORY_BLOCK_OFFSET_ST +`SHARED_MEMORY_LOG_WORDS_PER_READ-1)
`define SHARED_MEMORY_INDEX_OFFSET_ST (`SHARED_MEMORY_BLOCK_OFFSET_ED + 1) `define SHARED_MEMORY_INDEX_OFFSET_ST (`SHARED_MEMORY_BLOCK_OFFSET_ED + 1)
`define SHARED_MEMORY_INDEX_OFFSET_ED (`SHARED_MEMORY_INDEX_OFFSET_ST + $clog2(`SHARED_MEMORY_HEIGHT)-1) `define SHARED_MEMORY_INDEX_OFFSET_ED (`SHARED_MEMORY_INDEX_OFFSET_ST + $clog2(`SHARED_MEMORY_HEIGHT)-1)

68
rtl/VX_lsu.v
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@@ -31,39 +31,63 @@ module VX_lsu (
); );
wire[`NT_M1:0][31:0] use_address;
wire[`NT_M1:0][31:0] use_store_data;
wire[`NT_M1:0] use_valid;
wire[2:0] use_mem_read;
wire[2:0] use_mem_write;
wire[4:0] use_rd;
wire[`NW_M1:0] use_warp_num;
wire[1:0] use_wb;
wire[31:0] use_pc;
wire zero = 0;
VX_generic_register #(.N(308)) lsu_buffer(
.clk (clk),
.reset(reset),
.stall(out_delay),
.flush(zero),
.in ({address , VX_lsu_req.store_data, VX_lsu_req.valid, VX_lsu_req.mem_read, VX_lsu_req.mem_write, VX_lsu_req.rd, VX_lsu_req.warp_num, VX_lsu_req.wb, VX_lsu_req.lsu_pc}),
.out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc })
);
genvar index; genvar index;
for (index = 0; index <= `NT_M1; index = index + 1) begin for (index = 0; index <= `NT_M1; index = index + 1) begin
assign VX_dcache_req.out_cache_driver_in_address[index] = address[index]; assign VX_dcache_req.out_cache_driver_in_address[index] = use_address[index];
assign VX_dcache_req.out_cache_driver_in_data[index] = VX_lsu_req.store_data[index]; assign VX_dcache_req.out_cache_driver_in_data[index] = use_store_data[index];
assign VX_dcache_req.out_cache_driver_in_valid[index] = (VX_lsu_req.valid[index]); assign VX_dcache_req.out_cache_driver_in_valid[index] = (use_valid[index]);
assign VX_mem_wb.loaded_data[index] = VX_dcache_rsp.in_cache_driver_out_data[index]; assign VX_mem_wb.loaded_data[index] = VX_dcache_rsp.in_cache_driver_out_data[index];
end end
assign VX_dcache_req.out_cache_driver_in_mem_read = VX_lsu_req.mem_read; assign VX_dcache_req.out_cache_driver_in_mem_read = use_mem_read;
assign VX_dcache_req.out_cache_driver_in_mem_write = VX_lsu_req.mem_write; assign VX_dcache_req.out_cache_driver_in_mem_write = use_mem_write;
assign VX_mem_wb.rd = VX_lsu_req.rd; assign VX_mem_wb.rd = use_rd;
assign VX_mem_wb.wb = VX_lsu_req.wb & {!VX_dcache_rsp.delay, !VX_dcache_rsp.delay}; assign VX_mem_wb.wb = use_wb & {!VX_dcache_rsp.delay, !VX_dcache_rsp.delay};
assign VX_mem_wb.wb_valid = VX_lsu_req.valid; assign VX_mem_wb.wb_valid = use_valid;
assign VX_mem_wb.wb_warp_num = VX_lsu_req.warp_num; assign VX_mem_wb.wb_warp_num = use_warp_num;
assign VX_mem_wb.mem_wb_pc = VX_lsu_req.lsu_pc; assign VX_mem_wb.mem_wb_pc = use_pc;
integer curr_t; // integer curr_t;
always @(negedge clk) begin // always @(negedge clk) begin
for (int curr_t = 0; curr_t < `NT; curr_t=curr_t+1) // for (int curr_t = 0; curr_t < `NT; curr_t=curr_t+1)
if ((VX_dcache_req.out_cache_driver_in_valid[curr_t]) && !out_delay) begin // if ((VX_dcache_req.out_cache_driver_in_valid[curr_t]) && !out_delay) begin
if (VX_dcache_req.out_cache_driver_in_mem_read != `NO_MEM_READ) begin // if (VX_dcache_req.out_cache_driver_in_mem_read != `NO_MEM_READ) begin
$display("Reading addr: %x val: %x", address[0], VX_mem_wb.loaded_data[0]); // $display("Reading addr: %x val: %x", address[0], VX_mem_wb.loaded_data[0]);
end // end
if (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) begin // if (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) begin
$display("Writing addr: %x val: %x", address[0], VX_dcache_req.out_cache_driver_in_data[0]); // $display("Writing addr: %x val: %x", address[0], VX_dcache_req.out_cache_driver_in_data[0]);
end // end
end // end
end // end
// wire zero_temp = 0; // wire zero_temp = 0;
// VX_generic_register #(.N(142)) register_wb_data // VX_generic_register #(.N(142)) register_wb_data

4
rtl/VX_warp_scheduler.v
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@@ -176,7 +176,7 @@ module VX_warp_scheduler (
if (update_use_wspawn) begin if (update_use_wspawn) begin
use_wsapwn[warp_to_schedule] <= 0; use_wsapwn[warp_to_schedule] <= 0;
thread_masks[warp_to_schedule] <= 1'b1; thread_masks[warp_to_schedule] <= 1;
end end
@@ -284,7 +284,7 @@ module VX_warp_scheduler (
wire real_use_wspawn = use_wsapwn[warp_to_schedule]; wire real_use_wspawn = use_wsapwn[warp_to_schedule];
assign warp_pc = real_use_wspawn ? use_wsapwn_pc : warp_pcs[warp_to_schedule]; assign warp_pc = real_use_wspawn ? use_wsapwn_pc : warp_pcs[warp_to_schedule];
assign thread_mask = (global_stall) ? 0 : (real_use_wspawn ? 1'b1 : thread_masks[warp_to_schedule]); assign thread_mask = (global_stall) ? 0 : (real_use_wspawn ? `NT'b1 : thread_masks[warp_to_schedule]);
assign warp_num = warp_to_schedule; assign warp_num = warp_to_schedule;
assign update_use_wspawn = use_wsapwn[warp_to_schedule] && !global_stall; assign update_use_wspawn = use_wsapwn[warp_to_schedule] && !global_stall;

2
rtl/shared_memory/VX_shared_memory.v
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@@ -49,7 +49,7 @@ reg[`NT_M1:0][31:0] temp_out_data;
reg [SM_BANKS - 1:0][$clog2(SM_HEIGHT) - 1:0] block_addr; reg [SM_BANKS - 1:0][$clog2(SM_HEIGHT) - 1:0] block_addr;
reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_wdata; reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_wdata;
reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_rdata; reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_rdata;
reg [SM_BANKS - 1:0][SM_LOG_WORDS_PER_READ:0] block_we; reg [SM_BANKS - 1:0][SM_LOG_WORDS_PER_READ-1:0] block_we;
wire send_data; wire send_data;

37814
runtime/mains/nlTest/vx_nl_main.dump
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runtime/mains/nlTest/vx_nl_main.elf
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runtime/mains/nlTest/vx_nl_main.hex
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17
runtime/mains/simple/vx_simple_main.c
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@@ -52,6 +52,7 @@ int main()
// Main is called with all threads active of warp 0 // Main is called with all threads active of warp 0
vx_tmc(1); vx_tmc(1);
vx_print_str("Simple Main\n"); vx_print_str("Simple Main\n");
@@ -69,6 +70,22 @@ int main()
vx_print_str("test_wspawn\n"); vx_print_str("test_wspawn\n");
test_wsapwn(); test_wsapwn();
vx_print_str("Shared Memory test\n");
unsigned * ptr = (unsigned *) 0xFFFF0000;
unsigned value = 0;
for (int i = 0; i < 5; i++)
{
*ptr = value;
unsigned read_valud = *ptr;
vx_printf("ptr: ", (unsigned) ptr);
vx_printf("Original Value: ", value);
vx_printf("Read Value: ", read_valud);
vx_print_str("-------------------\n");
value++;
ptr++;
}
vx_print_str("vx_spawnWarps mat_add_kernel\n"); vx_print_str("vx_spawnWarps mat_add_kernel\n");
mat_add_args_t arguments; mat_add_args_t arguments;

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runtime/mains/simple/vx_simple_main.dump
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runtime/mains/simple/vx_simple_main.elf
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323
runtime/mains/simple/vx_simple_main.hex
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@@ -1,6 +1,6 @@
:0200000480007A :0200000480007A
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@@ -16,130 +16,148 @@
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:10001000340000003500000036000000370000000A :10001000340000003500000036000000370000000A
@@ -159,30 +177,35 @@
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43
runtime/newlib/newlib.c
View File

@@ -27,7 +27,12 @@ void upload(char ** ptr, char * src, int size)
{ {
char * drain = *ptr; char * drain = *ptr;
*((int *) drain) = size; // *((int *) drain) = size;
char * size_ptr = (char *) size;
drain[0] = size_ptr[0];
drain[1] = size_ptr[1];
drain[2] = size_ptr[2];
drain[3] = size_ptr[3];
drain += 4; drain += 4;
@@ -46,11 +51,19 @@ void download(char ** ptr, char * drain)
char * src = *ptr; char * src = *ptr;
int size; int size;
size = *((int *) src);
// size = *((int *) src);
char * size_ptr = (char *) size;
size_ptr[0] = src[0];
size_ptr[1] = src[1];
size_ptr[2] = src[2];
size_ptr[3] = src[3];
src += 4; src += 4;
vx_printf("newlib.c: Size of download: ", size); // vx_printf("newlib.c: Size of download: ", size);
vx_printf("newlib.c: Real size: ", sizeof(struct stat)); // vx_printf("newlib.c: Real size: ", sizeof(struct stat));
for (int i = 0; i < size; i++) for (int i = 0; i < size; i++)
{ {
@@ -79,12 +92,24 @@ int _fstat(int file, struct stat * st)
char * read_buffer = (char *) FILE_IO_READ; char * read_buffer = (char *) FILE_IO_READ;
struct stat newSt; unsigned value;
download((char **) &read_buffer, (char *) &value);
download((char **) &read_buffer, (char *) &newSt); st->st_mode = value;
download((char **) &read_buffer, (char *) &value);
st->st_mode = S_IFCHR; st->st_dev = value;
// download((char **) &read_buffer, (char *) &value);
// st->st_uid = value;
// download((char **) &read_buffer, (char *) &value);
// st->st_gid = value;
// download((char **) &read_buffer, (char *) &value);
// st->st_size = value;
// download((char **) &read_buffer, (char *) &value);
// st->st_blksize = value;
// download((char **) &read_buffer, (char *) &value);
// st->st_blocks = value;
// st->st_mode = S_IFCHR;
// st->st_mode = 33279;
vx_printf("st_mode: ", st->st_mode); vx_printf("st_mode: ", st->st_mode);
vx_printf("st_dev: ", st->st_dev); vx_printf("st_dev: ", st->st_dev);

1
simX/core.cpp
View File

@@ -101,7 +101,6 @@ void Harp::reg_doWrite(Word cpuId, Word regNum) {
Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id): Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id):
a(a), iDec(d), mem(mem), steps(4) a(a), iDec(d), mem(mem), steps(4)
{ {
release_warp = false; release_warp = false;
foundSchedule = true; foundSchedule = true;
schedule_w = 0; schedule_w = 0;

51
simX/instruction.cpp
View File

@@ -82,7 +82,8 @@ Word signExt(Word w, Size bit, Word mask) {
void upload(unsigned * addr, char * src, int size, Warp & c) void upload(unsigned * addr, char * src, int size, Warp & c)
{ {
// c.core->mem.write(current_addr, reg[rsrc[1]] & 0x000000FF, c.supervisorMode, 1);
cerr << "WRITING FINAL: " << *src << " size: " << size << "\n";
unsigned current_addr = *addr; unsigned current_addr = *addr;
@@ -93,6 +94,7 @@ void upload(unsigned * addr, char * src, int size, Warp & c)
for (int i = 0; i < size; i++) for (int i = 0; i < size; i++)
{ {
unsigned value = src[i] & 0x000000FF; unsigned value = src[i] & 0x000000FF;
cerr << "UPLOAD: (" << hex << current_addr << dec << ") = " << hex << ( value) << dec << "\n";
c.core->mem.write(current_addr, value, c.supervisorMode, 1); c.core->mem.write(current_addr, value, c.supervisorMode, 1);
current_addr += 1; current_addr += 1;
} }
@@ -155,13 +157,18 @@ void trap_to_simulator(Warp & c)
unsigned read_buffer = 0x71000000; unsigned read_buffer = 0x71000000;
unsigned write_buffer = 0x72000000; unsigned write_buffer = 0x72000000;
// cerr << "RAW READ BUFFER:\n"; cerr << "RAW READ BUFFER:\n";
// for (int i = 0; i < 10; i++) for (int i = 0; i < 10; i++)
// { {
// unsigned new_addr = read_buffer + (4*i); unsigned new_addr = read_buffer + (4*i);
// unsigned data_read = c.core->mem.read(new_addr, c.supervisorMode); unsigned data_read = c.core->mem.read(new_addr, c.supervisorMode);
// cerr << hex << new_addr << ": " << data_read << "\n"; cerr << hex << new_addr << ": " << data_read << "\n";
// } }
for (int j = 0; j < 1024; j+=1)
{
c.core->mem.write((write_buffer+j), 0, c.supervisorMode, 1);
}
int command; int command;
download(&read_buffer, (char *) &command, c); download(&read_buffer, (char *) &command, c);
@@ -219,18 +226,26 @@ void trap_to_simulator(Warp & c)
fprintf(stderr, "------------------------\n"); fprintf(stderr, "------------------------\n");
fprintf(stderr, "Size of struct: %x\n", sizeof(struct stat)); fprintf(stderr, "Size of struct: %x\n", sizeof(struct stat));
fprintf(stderr, "st_mode: %d\n", st.st_mode); fprintf(stderr, "st_mode: %x\n", st.st_mode);
fprintf(stderr, "st_dev: %d\n", st.st_dev); fprintf(stderr, "st_dev: %x\n", st.st_dev);
fprintf(stderr, "st_ino: %d\n", st.st_ino); fprintf(stderr, "st_ino: %x\n", st.st_ino);
fprintf(stderr, "st_uid: %d\n", st.st_uid); fprintf(stderr, "st_uid: %x\n", st.st_uid);
fprintf(stderr, "st_gid: %d\n", st.st_gid); fprintf(stderr, "st_gid: %x\n", st.st_gid);
fprintf(stderr, "st_rdev: %d\n", st.st_rdev); fprintf(stderr, "st_rdev: %x\n", st.st_rdev);
fprintf(stderr, "st_size: %d\n", st.st_size); fprintf(stderr, "st_size: %x\n", st.st_size);
fprintf(stderr, "st_blksize: %d\n", st.st_blksize); fprintf(stderr, "st_blksize: %x\n", st.st_blksize);
fprintf(stderr, "st_blocks: %d\n", st.st_blocks); fprintf(stderr, "st_blocks: %x\n", st.st_blocks);
fprintf(stderr, "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n"); fprintf(stderr, "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n");
upload(&write_buffer, (char *) &st, sizeof(struct stat), c); upload(&write_buffer, (char *) &st.st_mode , sizeof(st.st_mode), c);
upload(&write_buffer, (char *) &st.st_dev , sizeof(st.st_dev), c);
// upload(&write_buffer, (char *) &st.st_uid , sizeof(st.st_uid), c);
// upload(&write_buffer, (char *) &st.st_gid , sizeof(st.st_gid), c);
// upload(&write_buffer, (char *) &st.st_size , sizeof(st.st_size), c);
// upload(&write_buffer, (char *) &st.st_blksize , sizeof(st.st_blksize), c);
// upload(&write_buffer, (char *) &st.st_blocks , sizeof(st.st_blocks), c);
// upload(&write_buffer, (char *) &st, sizeof(struct stat), c);
cerr << "RAW Write BUFFER:\n"; cerr << "RAW Write BUFFER:\n";
unsigned original_write_buffer = 0x72000000; unsigned original_write_buffer = 0x72000000;

1929
syn/vortex_syn.log
View File

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