Added a pipeline stage + fixed SM param errors

2019-11-13 12:25:28 -05:00
parent 7f7d17d176
commit 70651f0340
15 changed files with 26390 additions and 24621 deletions
--- a/rtl/shared_memory/VX_shared_memory.v
+++ b/rtl/shared_memory/VX_shared_memory.v
@@ -49,7 +49,7 @@ reg[`NT_M1:0][31:0] temp_out_data;
 reg [SM_BANKS - 1:0][$clog2(SM_HEIGHT) - 1:0] block_addr;
 reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_wdata;
 reg [SM_BANKS - 1:0][SM_WORDS_PER_READ-1:0][31:0] block_rdata;
-reg [SM_BANKS - 1:0][SM_LOG_WORDS_PER_READ:0] block_we;
+reg [SM_BANKS - 1:0][SM_LOG_WORDS_PER_READ-1:0] block_we;

 wire send_data;