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added support for write-through cache, removed cache snooping support

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This commit is contained in:
Blaise Tine
2020-12-23 23:51:02 -08:00
parent d956e268b9
commit 703a861fe9
55 changed files with 1077 additions and 2178 deletions
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80
hw/rtl/VX_core.v
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@@ -24,28 +24,17 @@ module VX_core #(
input wire [`XDRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// Snoop request
input wire snp_req_valid,
input wire [`DDRAM_ADDR_WIDTH-1:0] snp_req_addr,
input wire snp_req_inv,
input wire [`DSNP_TAG_WIDTH-1:0] snp_req_tag,
output wire snp_req_ready,
// CSR request
input wire csr_req_valid,
input wire [11:0] csr_req_addr,
input wire csr_req_rw,
input wire [31:0] csr_req_data,
output wire csr_req_ready,
output wire snp_rsp_valid,
output wire [`DSNP_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready,
// CSR I/O request
input wire csr_io_req_valid,
input wire [11:0] csr_io_req_addr,
input wire csr_io_req_rw,
input wire [31:0] csr_io_req_data,
output wire csr_io_req_ready,
// CSR I/O response
output wire csr_io_rsp_valid,
output wire [31:0] csr_io_rsp_data,
input wire csr_io_rsp_ready,
// CSR response
output wire csr_rsp_valid,
output wire [31:0] csr_rsp_data,
input wire csr_rsp_ready,
// Status
output wire busy,
@@ -81,27 +70,6 @@ module VX_core #(
//--
VX_cache_snp_req_if #(
.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
.SNP_TAG_WIDTH(`DSNP_TAG_WIDTH)
) dcache_snp_req_if();
VX_cache_snp_rsp_if #(
.SNP_TAG_WIDTH(`DSNP_TAG_WIDTH)
) dcache_snp_rsp_if();
assign dcache_snp_req_if.valid = snp_req_valid;
assign dcache_snp_req_if.addr = snp_req_addr;
assign dcache_snp_req_if.invalidate = snp_req_inv;
assign dcache_snp_req_if.tag = snp_req_tag;
assign snp_req_ready = dcache_snp_req_if.ready;
assign snp_rsp_valid = dcache_snp_rsp_if.valid;
assign snp_rsp_tag = dcache_snp_rsp_if.tag;
assign dcache_snp_rsp_if.ready = snp_rsp_ready;
//--
VX_cache_core_req_if #(
.NUM_REQS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
@@ -135,7 +103,7 @@ module VX_core #(
) pipeline (
`SCOPE_BIND_VX_core_pipeline
`ifdef PERF_ENABLE
.perf_memsys_if (perf_memsys_if),
.perf_memsys_if (perf_memsys_if),
`endif
.clk(clk),
@@ -171,17 +139,17 @@ module VX_core #(
.icache_rsp_tag (core_icache_rsp_if.tag),
.icache_rsp_ready (core_icache_rsp_if.ready),
// CSR I/O request
.csr_io_req_valid (csr_io_req_valid),
.csr_io_req_rw (csr_io_req_rw),
.csr_io_req_addr (csr_io_req_addr),
.csr_io_req_data (csr_io_req_data),
.csr_io_req_ready (csr_io_req_ready),
// CSR request
.csr_req_valid (csr_req_valid),
.csr_req_rw (csr_req_rw),
.csr_req_addr (csr_req_addr),
.csr_req_data (csr_req_data),
.csr_req_ready (csr_req_ready),
// CSR I/O response
.csr_io_rsp_valid (csr_io_rsp_valid),
.csr_io_rsp_data (csr_io_rsp_data),
.csr_io_rsp_ready (csr_io_rsp_ready),
// CSR response
.csr_rsp_valid (csr_rsp_valid),
.csr_rsp_data (csr_rsp_data),
.csr_rsp_ready (csr_rsp_ready),
// Status
.busy(busy),
@@ -195,7 +163,7 @@ module VX_core #(
) mem_unit (
`SCOPE_BIND_VX_core_mem_unit
`ifdef PERF_ENABLE
.perf_memsys_if (perf_memsys_if),
.perf_memsys_if (perf_memsys_if),
`endif
.clk (clk),
@@ -209,10 +177,6 @@ module VX_core #(
.core_icache_req_if (core_icache_req_if),
.core_icache_rsp_if (core_icache_rsp_if),
// Dcache Snoop
.dcache_snp_req_if (dcache_snp_req_if),
.dcache_snp_rsp_if (dcache_snp_rsp_if),
// DRAM
.dram_req_if (dram_req_if),
.dram_rsp_if (dram_rsp_if)